PC87373 datasheet(51/174 Pages) NSC

No. de pieza	PC87373

Descripción Electrónicos	LPC SuperI/O with Glue Functions

PDF	174 Pages

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Fabricante Electrónico	NSC [National Semiconductor (TI)]

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51 / 174 page

3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.8.4

Drive ID Register

This register is reset to 00h. This register controls bits 5 and 4 of the TDR register in Enhanced mode.

Power Well: VDD3

Location:

Index F1h

Type:

R/W

Usage Hints: Some BIOS implementations support FDDs with automatic media sense; in this case, bit 5 of TDR register in

Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic

media sense, bits 1 and/or 3 of the Drive ID register must be set to 1 (to indicate non-valid media sense). When Drive 0 or

Drive 1 is selected, the Drive ID bit is reflected on bit 5 of TDR register in Enhanced mode.

Bit

76543210

Name

Reserved

Drive 1 ID

Drive 0 ID

Reset

00000000

Bit

Description

7-4

Reserved.

3-2

Drive 1 ID. When drive 1 is accessed, these bits are reﬂected on bits 5-4 of the TDR register, respectively.

1-0

Drive 0 ID. When drive 0 is accessed, these bits are reﬂected on bits 5-4 of the TDR register, respectively.

PC87373 Datasheet(PDF) 51 Page - National Semiconductor (TI)