LM2647 datasheet(21/25 Pages) NSC

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Application Information (Continued)

TABLE 1. Losses and Efficiency

Upper

Lower

Pcond (mW)

Psw (mW)

611

PFET (mW)

665

128

IC (mW)

Pind (mW)

257

Ptotal (mW)

1078

Pout (=VoxIo) (mW)

15000

93%

Vo=5V, Io=3A,Vin=20V, f=300kHz, DCR=26m

Ω, Si4828DY.

Typical efficiency curves for different input voltages are avail-

able under Typical Performance Characteristics.

LAYOUT GUIDELINES

For a deeper understanding of Buck converters and the

‘critical traces’ please see Application Note AN-1229 at http://

power.national.com.

Figure 14 is based on such an understanding of the critical

sections and also the pin functions of the LM2647. Refer to

the Typical Applications circuit and the LM2647 TSSOP pi-

nouts to understand the layout suggestions more thoroughly.

The components shown in Figure 14 are most critical and

must be placed close to the device and connected onto a

ground island on the component side. Several vias can then

connect to the ground plane at the locations indicated. The

FETs are positioned close to the controller and are also very

close to each other to minimize inductances.

After the critical components are placed, the resistor to the

frequency adjust pin (R19) must also be placed close to the

IC connecting to SGND. This will reduce noise pickup and

jitter.

The feedback trace can also pick up noise and it must be

routed away from sources of noise/EMI, particularly the

FETs and inductors.

Enough copper area must be left around the FETs for ther-

mal dissipation. More details on this are also provided in

AN-1229.

Note that the current limit detector circuit compares the

voltage on the ILIM pin with respect to the PGND pin.

Therefore, if the power ground is noisy it can lead to errone-

ous triggering of the current limit detector. This will manifest

itself as an inability to meet the load requirement despite

oversizing the current limit resistor. It can also lead to failure

of the output to recover after encountering an overload con-

dition. Therefore, it is strongly recommended that a solid

ground plane be created as the first internal plane right

below the component side.Several vias should be gener-

ously placed to connect the ground nodes of the component

layer to this ground plane.

SETTING OUTPUT VOLTAGE

From the Typical Application circuit on Page 1, it can be seen

that R15 and R16 are used to set V

O2 whereas R21 and R22

set V

O1. For either channel, calling the upper resistor (con-

nected to one end of the droop resistor) R

U and the lower

resistor (connected to ground) R

L the following equation is

applicable.

Therefore from the Bill of Material:

For channel #1 (V

O1 =5V),

U = R21 = 43.2k

L = R22 = 5.9k

For channel #1 (V

O2 = 3.3V),

U = R15 = 43.2k

L = R16 = 9.53k

This is as per the requirement of the primary end-application.

Other output voltage values are possible by adjusting the

resistor ratios (but note that there are maximum duty cycle

constraints as stated in Electrical Characteristics table)

which will limit the range of output voltages achievable. Note

that the upper resistor is involved in fixing the gain of the

error amplifier, and therefore its value has been set to an

‘optimum’ value of 43.2k for both channels. This value helps

in achieving good step response and ensuring stability.

Therefore, in general, only the lower resistor should be

adjusted. However the more experienced designer can judi-

ciously use the open-loop gain information provided in the

next section, to change both upper and lower resistor values

if required.

20056343

FIGURE 14. Critical Component placement (TSSOP)

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