AM79C970 datasheet(117/168 Pages) AMD

117 / 168 page

AMD

P R E L I M I N A R Y

1-984

Am79C970

gives a default linear burst length

of 4 transfers = 001b x 4.

BCR19: EEPROM Control and Status Register

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

PVALID

EEPROM Valid status bit. This

bit is read only by the host. A

value of ONE in this bit indicates

that a PREAD operation has oc-

curred, and that 1) there is an

EEPROM

connected

the

PCnet-PCI controller Microwire

interface pins and 2) the contents

read from the EEPROM have

passed the checksum verifica-

tion operation.

A value of ZERO in this bit indi-

cates that the contents of the

EEPROM are different from the

contents of the applicable PCnet-

PCI controller on-board registers

and/or that the checksum for the

entire 36 bytes of EEPROM is in-

correct

or that no EEPROM is

connected to the Microwire inter-

face pins.

PVALID is set to ZERO during

H_RESET and is unaffected by

S_RESET or the STOP bit. How-

ever, following the H_RESET op-

eration, an automatic read of the

EEPROM will be performed.

Just as is true for the normal

PREAD command, at the end of

this automatic read operation,

the PVALID bit may be set to

ONE. Therefore, H_RESET will

set the PVALID bit to ZERO at

first, but the automatic EEPROM

read operation may later set

PVALID to a ONE.

If PVALID becomes ZERO fol-

lowing an EEPROM read opera-

tion

(either

automatically

generated after H_RESET, or re-

quested through PREAD), then

all

EEPROM-programmable

BCR locations will be reset to

their H_RESET values. The con-

tent of the APROM locations,

however, will not be cleared.

If no EEPROM is present at the

EESK, EEDI and EEDO pins,

then all attempted PREAD com-

mands will terminate early and

PVALID will NOT be set. This ap-

plies to the automatic read of the

EEPROM after H_RESET as

well as to host–initiated PREAD

commands.

PREAD

EEPROM Read command bit.

When this bit is set to a ONE by

the host, the PVALID bit (BCR19,

bit 15) will immediately be reset

to a ZERO and then the PCnet-

PCI controller will perform a read

operation of 36 bytes from the

EEPROM through the Microwire

interface. The EEPROM data

that is fetched during the read will

be stored in the appropriate inter-

nal registers on board the PCnet-

PCI controller. Upon completion

of the EEPROM read operation,

the PCnet-PCI controller will as-

sert the PVALID bit. EEPROM

contents will be indirectly acces-

sible to the host through I/O read

accesses to the APROM (offsets

0h through Fh) and through I/O

read accesses to other EEPROM

programmable registers. Note

that I/O read accesses from

these locations will not actually

access the EEPROM itself, but

instead will access the PCnet-

PCI controllers internal copy of

the EEPROM contents. I/O write

accesses to these locations may

change the PCnet-PCI controller

contents,

but

the

EEPROM locations will not be af-

fected. EEPROM locations may

be accessed directly through

BCR19.

At the end of the read operation,

the PREAD bit will automatically

be reset to a ZERO by the PCnet-

PCI controller and PVALID will

bet

set,

provided

that

EEPROM

existed

the

Microwire interface pins and that

the checksum for the entire 36

bytes of EEPROM was correct.

Note that when PREAD is set to a

ONE, then the PCnet-PCI con-

troller will no longer respond to

I/O accesses directed toward it,

until the PREAD operation has

completed

successfully.

The

PCnet-PCI controller will termi-

nate these I/O accesses with the

assertion of

DEVSEL and STOP

while

TRDY is not asserted, sig-

naling to the initiator to retry the

access at a later time.

If a PREAD command is given to

the PCnet-PCI controller but no

EEPROM is attached to the

Microwire interface pins, then the

AM79C970 Datasheet(PDF) 117 Page - Advanced Micro Devices

AM79C970 Datasheet(HTML) 117 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL