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MB91F467DA Datasheet(PDF) 34 Page - Cypress Semiconductor

No. de pieza MB91F467DA
Descripción Electrónicos  32-bit RISC, load/store architecture, five-stage pipeline
PDF  137 Pages
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Fabricante Electrónico  CYPRESS [Cypress Semiconductor]
Página de inicio  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB91F467DA Datasheet(HTML) 34 Page - Cypress Semiconductor

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Document Number: 002-04613 Rev. *A
Page 34 of 137
MB91460D Series
9.3.2 Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation)
for Flash read and write access.
Flash read timing settings (synchronous read)
Flash write timing settings (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
Remark
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 96 MHz
1
1
3
-
4
to 100 MHz
1
1
3
-
4
not available on MB91F467Dx
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
Remark
to 32 MHz
1
-
-
0
4
to 48 MHz
1
-
-
0
5
to 64 MHz
1
-
-
0
6
to 96 MHz
1
-
-
0
7
to 100 MHz
1
-
-
0
7
not available on MB91F467Dx



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