ADP2443ACPZN-R7 datasheet(23/25 Pages) AD

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ADP2443

Data Sheet

Rev. 0 | Page 22 of 24

PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good PCB layout is essential for obtaining the best performance

from the ADP2443. Poor PCB layout can degrade the output

regulation, as well as the electromagnetic interface (EMI) and

electromagnetic compatibility (EMC) performance. Figure 42

shows an example of a good PCB layout for the ADP2443. For

optimum layout, refer to the following guidelines:



Use separate analog ground planes and power ground planes.

Connect the ground reference of sensitive analog circuitry,

such as output voltage divider components, compensation

components, frequency setting components, and soft start

capacitor, to analog ground (GND). In addition, connect the

ground reference of the power components, such as input

and output capacitors, to power ground (PGND). Connect

both ground planes to the exposed GND pad of the

ADP2443.



Place the input capacitor, inductor, and output capacitor as

close as possible to the IC, and use short traces.



Ensure that the high current loop traces are as short and as

wide as possible. Make the high current path from the input

capacitor through the inductor, the output capacitor, and the

power ground plane back to the input capacitor as short as

possible. To accomplish this, ensure that the input and output

capacitors share a common power ground plane.

In addition, ensure that the high current path from the power

ground plane through the inductor and output capacitor

back to the power ground plane is as short as possible by

tying the PGND pins of the ADP2443 to the PGND plane

as close as possible to the input and output capacitors.



Connect the exposed GND pad of the ADP2443 to a large,

external copper ground plane to maximize its power

dissipation capability and minimize junction temperature.

In addition, connect the exposed SW pad to the SW pins

of the ADP2443, using short, wide traces; or connect the

exposed SW pad to a large copper plane of the switching

node for high current flow.



Place the feedback resistor divider as close as possible to

the FB pin to prevent noise pickup. Minimize the length of

the trace that connects the top of the feedback resistor divider

to the output while keeping the trace away from the high

current traces and the switching node to avoid noise

pickup. To reduce noise pickup further, place an analog

ground plane on either side of the FB trace and ensure that

the trace is as short as possible to reduce the parasitic

capacitance pickup.

RRAMP

RBOT

RTOP

COUT

CIN

VOUT

VIN

CBST

CSS

CVREG

GND

PGND

COMP

VREG

RT/SYNC

PGOOD

RAMP

PVIN

ADP2443

BST

Figure 41. High Current Path in the PCB Circuit

GND

PVIN

ANALOG GROUND PLANE

RRAMP

PVIN

BST

CBST

PGND

COMP

VREG

GND

OUTPUT

CAPACITOR

INDUCTOR

POWER GROUND PLANE

INPUT

BYPASS CAP

VIA

BOTTOM LAYER TRACE

COPPER PLANE

INPUT

BULK CAP

VOUT

RTOP

CVREG

Figure 42. Recommended PCB Layout

ADP2443ACPZN-R7 Datasheet(PDF) 23 Page - Analog Devices

ADP2443ACPZN-R7 Datasheet(HTML) 23 Page - Analog Devices

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