UT80C196 datasheet(20/42 Pages) AEROFLEX

20 / 42 page

TUO

BHE

Low

Byte High Enable. The assertion of the BHE signal will occur

for all 16-bit word writes, and high byte writes in both 8- and 16-

bit wide bus cycles.

Setting CCR.2 = 1 enables the BHE function of pin 41.

TUO

WRH

Low

Write High. The WRH signal is asserted for high byte writes,

and word writes for 16-bit wide bus cycles. Additionally, WRH

is asserted for all write operations when using an 8-bit wide bus

cycle.

Setting CCR.2 = 0 enables the WRH function of pin 41.

P2.4

---

Port 2 Pin 4. An input only port pin that is read at location 10h

of HWindow 0.

T2RST

High

Timer 2 Reset. Asserting the T2RST signal will reset Timer 2.

To enable the T2RST function of pin 42, set IOC0.3 = 1 and

IOC0.5 = 0.

READY

High

READY input. The READY signal is used to lengthen memory

cycles by inserting “wait states” for interfacing to slow peripher-

als. When the READY signal is high, no “wait states” are gener-

ated, and the CPU operation continues in a normal fashion. If

READY is low during the falling edge of CLKOUT, the mem-

ory controller inserts “wait states” into the memory cycle. “Wait

state” generation will continue until a falling edge of CLKOUT

detects READY as logically high, or until the number of “wait

states” is equal to the number programmed into CCR.4 and

CCR.5.

Note: The READY signal is only used for external memory

accesses, and is functional during the CCR fetch.

P2.3

---

Port 2 Pin 3. An input only port pin that is read at location 10h

of HWindow 0.

T2CLK

---

Timer 2 Clock input. Setting IOC0.7 = 0 and IOC3.0 = 0

enables this pin as the external clock source for Timer 2.

IOC0.7:

IOC3.0:

Timer 2 Clock Source:

Internal Clock Source

P2.3 External Clock Source

HSI.1 External Clock Source

TUB

AD15

---

Bit 15 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

UT80C196 Datasheet(PDF) 20 Page - Aeroflex Circuit Technology

UT80C196 Datasheet(HTML) 20 Page - Aeroflex Circuit Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Descarga

Enlace URL