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CS7808 Datasheet(PDF) 20 Page - Cirrus Logic |
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CS7808 Datasheet(HTML) 20 Page - Cirrus Logic |
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20 / 52 page ![]() CS7808 20 3.2.11 System Functions • 208-pin PQFP packages • All I/O pins are 3 V with 5 V tolerance • Advanced 0.25 micron CMOS technology • Internal processors run at 81 MHz • Supports Low Power modes and clock shutoff 3.3 RISC Processor The CS7808 includes two powerful, proprietary 32-bit RISC processors, RISC0 and RISC1, with optimizing C compiler support and source level de- bugger. The RISC processors fully support many Real Time Operation Systems (RTOS). In addition to being compatible with the standard MIPS® R3000® instruction set, the RISC proces- sors also have a MAC engine, which performs mul- tiply/accumulate in 2 cycles in a pipelined fashion with C support, effectively achieving single cycle throughout. 3.4 DSP Processor The CS7808 contains a proprietary digital signal processor (DSP), which is optimized for audio ap- plications. The DSP performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. There are 32 general- purpose registers, and eight independent address generation registers, featuring: linear and circular buffer operations, and dual operand read from memory. The multiply-accumulator has single-cy- cle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking opera- tions. The interface to main memory is designed for handling flexible block sizes and skip counts. 3.5 Memory Control The DRAM Interface performs the SDRAM con- trol and arbitration functions for all the other mod- ules in the CS7808. The DRAM interface services and arbitrates a number of clients and stores their code and/or data within the local memory. This ar- bitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. The DRAM Interface supports up to 32 Mbytes. For a typical application, the CS7808 requires 8 Mbytes memory space. Sharing the same interface, CS7808 also supports FLASH ROM,OTP, or maskROM interface. Code is stored in ROM. After the system is booted, the code is shadowed inside SDRAM for execution. The FLASH ROM interface is provided so that the code can be upgraded in the field once the commu- nications channel is established (via modem port, CD-R, or serial port). Utility software will be pro- vided to debug and upgrade code for the system manufacturer. 3.6 Dataflow Control (DMA) The DMA controller moves data between the exter- nal memory and internal memory. The external memory address can be specified using a register, or in FIFO mode, using start and end address regis- ters. Separate start/end address registers are used for DMA read and write operations. The DMA in- terface also has a block transfer function, which al- lows for the transfer of one block of data from one external memory location to another external mem- ory location. In effect, this feature combines a DMA read and write into one operation. In addi- tion, the DMA write operation allows for byte, short, word, and other types of masking. 3.7 System Control Functions The system control functions are used to coordinate the activities of the multiple processors, and to pro- vide the supporting system operations. Four 32-bit communication registers are available for inter- processor communication, and eight semaphore registers are used for resource locking. Timers are available for general-purpose functions, as well as more specialized functions such as watchdog tim- ers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. An I2Cmaster allows for control of other I2C devices,suchasa video encoder. An I2C slave port shares the same pins, and can be used for debug functions. Inter- |
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