TMS320C6412 datasheet(6/159 Pages) TI

6 / 159 page

Revision History

April 2003 − Revised June 2004

SPRS219D

PAGE(s)

NO.

ADDS/CHANGES/DELETES

113

Asynchronous Memory Timing section:

Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table:

Deleted “The AARDY signal is recognized in the cycle for which the setup and hold time is met.” from the AARDY signal

footnote

Added “The AARDY signal is only recognized two cycles before the end of the programmed strobe time and while AARDY is

low, the strobe time is extended cycle-by-cycle. When AARDY is recognized low, the end of the strobe time is two cycles

after AARDY is recognized high.” to the AARDY footnote

126

HOLD/HOLDA Timing section:

Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module table:

Changed parameter NO. 3 from “toh(HOLDAL-HOLDL)” to “th(HOLDAL-HOLDL)”

128−129

Reset Timing section:

Timing Requirements for Reset table:

Changed the MIN value of parameter No. 17, th(boot) from “4E or 4C” ns to “4P” ns

Added the associated “P note” footnote

Added parameter NO. 18, “td(PCLK−RSTH) Delay time, PCLK active to RESET high” with a MIN value of “32N” ns

Changed parameter NO. 18 description from “td(PCLK−RSTH) Delay time, PCLK active to RESET high” to “tsu(PCLK-RSTH),

Setup time, PCLK active before RESET high”

Added associated footnote to identify “N” and restraints

Switching Characteristics Over Recommended Operating Conditions During Reset table:

Updated footnote symbols

Figure 10−1, Reset Timing:

Updated figure to include the PCLK signal and parameter 18

Added “MAC_EN” to the “If AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5 pins ...” footnote

Added/Updated the “Boot and Device Configurations Inputs (during reset) include: ...” footnote

133

Host-Port Interface (HPI) Timing section:

Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles table:

Added “mode, 2nd half-word” to parameter NO. 16 “td(HSTBL-HDV), Delay time, HSTROBE low to HD valid (HPI16 only)”

141−142

Multichannel Buffered Serial Port (McBSP) Timing section:

Timing Requirements for McBSP table:

Added the MIN value of “or 6.67” ns to No. 2, tc(CKRX) parameter

Changed/updated the associated footnote

Switching Characteristics Over Recommended Operating Conditions for McBSP table:

Added the MIN value of “or 6.67” ns to No. 2, tc(CKRX) parameter

Changed/updated the associated footnote

149

Ethernet Media Access Controller (EMAC) Timing section:

Timing Requirements for MRCLK table:

Deleted parameter No. 4, “tt(MRCLK), Transition time, MRCLK”

Deleted associated reference points for rise and fall transitions footnote

Updated/changed Figure 16−1, MRCLK Timing (EMAC − Receive)

149

Ethernet Media Access Controller (EMAC) Timing section:

Timing Requirements for MTCLK table:

Deleted parameter No. 4, “tt(MTCLK), Transition time, MTCLK”

Deleted associated reference points for rise and fall transitions footnote

Updated/changed Figure 16−2, MTCLK Timing (EMAC − Transmit)

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