34

Am29F032B

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does

the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 5 for further

information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTIC

Note: Includes all pins except V

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

1

8

sec

Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time

64

sec

Byte Programming Time

7

300

µs

Excludes system-level overhead

(Note 5)

Chip Programming Time (Note 3)

28.8

86.4

sec

Description

Min

Max

Input Voltage with respect to V

–1.0 V

V

V

–100 mA

+100 mA

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

C

IN

Input Capacitance

V

6

7.5

pF

C

OUT

Output Capacitance

V

8.5

12

pF

C

IN2

Control Pin Capacitance

V

7.5

9

pF

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

°C

10

Years

125

°C

20

Years