30

Symbol

Parameter

Conditions

Min

Max

Units

Address Strobe Width

60

ns

Address Hold Time

0

ns

RD RD Delay from Address

(Note 1)

30

ns

Address Setup Time

60

ns

WR WR Delay from Address

(Note 1)

30

ns

Chip Select Hold Time

0

ns

Chip Select Setup Time

60

ns

RD RD Delay from Chip Select

(Note 1)

30

ns

WR WR Delay from Select

(Note 1)

30

ns

Data Hold Time

30

ns

Data Setup Time

30

ns

RD RD to Floating Data Delay

100 pF loading (Note 3)

0

100

ns

Master Reset Pulse Width

5000

ns

Address Hold Time from RD RD

(Note 1)

20

ns

Read Cycle Delay

125

ns

Chip Select Hold Time from RD RD

(Note 1)

20

ns

RD RD Strobe Width

125

ns

RD RD to Driver EnableDisable

100 pF loading (Note 3)

60

ns

Delay from RD RD to Data

100 pF loading

60

ns

Address Hold Time from WR WR

(Note 1)

20

ns

Write Cycle Delay

150

ns

Chip Select Hold Time from WR WR

(Note 1)

20

ns

WR WR Strobe Width

100

ns

Duration of Clock High Pulse

External Clock (8 Max)

55

ns

Duration of Clock Low Pulse

External Clock (8 Max)

55

ns

RC

280

ns

WC

280

ns

Baud Generator

N

Baud Divisor

1

Baud Output Positive Edge Delay

100 pF Load

175

ns

Baud Output Negative Edge Delay

100 pF Load

175

ns

Baud Output Up Time

75

ns

Baud Output Down Time

100

ns

Receiver

Delay from Active Edge

ns

of RD to Reset Interrupt

Delay from RD RD

100 pF Load

(RD RBRor RD LSR)

1000

ns

to Reset Interrupt

Delay from RD RBR

290

ns

to RXRDY Inactive

Delay from RCLK to Sample Time

2000

ns

Delay from Stop to Set Interrupt

(Note 2)

1

RCLK

Cycles

Note 1

Applicable only when ADS is tied low

Note 2

will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes these

indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs

Note 3

Note 4

These specifications are preliminary

4