PC87309VLJ datasheet(104/192 Pages) NSC

104 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

104

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5.4

UART MODES – DETAILED DESCRIPTION

The UART modes support serial data communications with a

remote peripheral device or modem using a wired interface.

The module provides receive and transmit channels that

can operate concurrently in full-duplex mode. This module

performs all functions required to conduct parallel data in-

terchange with the system and composite serial data ex-

change with the external data channel, including:

Format conversion between the internal parallel data

format and the external programmable composite seri-

al format. See Figure 5-2.

Serial data timing generation and recognition

Parallel data interchange with the system using a

choice of bi-directional data transfer mechanisms

Status monitoring for all phases of the communica-

tions activity

The module supplies modem control registers, and a prior-

itized interrupt system for efficient interrupt handling.

5.4.1

16450 or 16550 UART Mode

The module defaults to 16450 mode after power up or reset.

UART 16550 mode is equivalent to 16450 mode, with the

addition of a 16-byte data FIFO for more efficient data I/O.

Transparent compatibility is maintained with this UART

mode in this module.

Despite the many additions to the basic UART hardware

and organization, the UART responds correctly to existing

software drivers with no software modification required.

When 16450 software initializes and addresses this mod-

ule, it will in always perform as a 16450 device.

Data transfer takes place by use of data buffers that inter-

face internally in parallel and with the external data channel

in a serial format. 16-byte data FIFOs may reduce host

overhead by enabling multiple-byte data transfers within a

single interrupt. With FIFOs disabled, this module is equiv-

alent to the standard 16450 UART. With FIFOs enabled, the

hardware functions as a standard 16550 UART.

The composite serial data stream interfaces with the data

channel through signal conditioning circuitry such as

TTL/RS232 converters, modem tone generators, etc.

Data transfer is accompanied by software-generated con-

trol signals, which may be utilized to activate the communi-

cations channel and “handshake” with the remote device.

These may be supplied directly by the UART, or generated

by control interface circuits such as telephone dialing and

answering circuits, etc.

FIGURE 5-2. Composite Serial Data

The composite serial data stream produced by the UART is

illustrated in Figure 5-2. A data word containing five to eight

bits is preceded by start bits and followed by an optional

parity bit and a stop bit. The data is clocked out, LSB first,

at a predetermined rate (the baud).

The data word length, parity bit option, number of start bits

and baud are programmable parameters.

The UART includes a programmable Baud Generator that

produces the baud clocks and associated timing signals for

serial communication.

The system can monitor this module status at any time. Sta-

tus information includes the type and condition of the trans-

fer operation in process, as well as any error conditions

(e.g., parity, overrun, framing, or break interrupt).

The module resources include modem control capability

and a prioritized interrupt system. Interrupts can be pro-

grammed to match system requirements, minimizing the

CPU overhead required to handle the communications link.

Programmable Baud Generator

This module contains a programmable Baud Generator that

generates the clock rates for serial data communication

(both transmit and receive channels). It divides its input

clock by any divisor value from 1 to 216 - 1. The output clock

frequency of the Baud Generator must be programmed to

be sixteen times the baud value. A 24 MHz input frequency

is divided by a prescale value (PRESL field of EXCR2 - see

page 121. Its default value is 13) and by a 16-bit program-

mable divisor value contained in the Baud Generator Divi-

sor High and Low registers (BGD(H) and BGD(L) - see page

119). Each divisor value yields a clock signal (BOUT) and a

further division by 16 produces the baud clock for the serial

data stream. It may also be output as a test signal when en-

abled (see bit 7 of EXCR1 on page 120.)

These user-selectable parameters enable the user to gen-

erate a large choice of serial data rates, including all stan-

dard baud rates. A list of baud rates and their settings

appears in Table 5-14 on page 119.

Module Operation

Before module operation can begin, both the communica-

tions format and baud must be programmed by the soft-

ware. The communications format is programmed by

loading a control byte into the LCR register, while the baud

is selected by loading an appropriate value into the Baud

Generator Divisor Registers and the divisor preselect val-

ues (PRESL) into EXCR2 (see page 121).

The software can read the status of the module at any time

during operation. The status information includes full or

empty state for both transmission and reception channels,

and any other condition detected on the received data

stream, like parity error, framing error, data overrun, or

break event.

5.4.2

Extended UART Mode

In Extended UART mode of operation, the module configu-

ration changes and additional features become available

which enhance UART capabilities.

The interrupt sources are no longer prioritized; they

are presented bit-by-bit in the EIR (see page 110).

An auxiliary status and control register replaces the

scratchpad register. It contains additional status and

control ﬂag bits (“Auxiliary Status and Control Register

(ASCR)” on page 117).

The TX_FIFO can generate interrupts when the number

of outgoing bytes in the TX_FIFO drops below a program-

mable threshold. In the Non-Extended UART modes, only

reception FIFOs have the thresholding feature.

DMA capability is available.

Interrupts occur when the transmitter becomes empty

or a DMA event occurs.

START -LSB- DATA 5-8 -MSB- PARITY

STOP

PC87309VLJ Datasheet(PDF) 104 Page - National Semiconductor (TI)

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