PC87309VLJ datasheet(108/192 Pages) NSC

108 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

108

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5.11.1

Receiver Data Port (RXD) or the Transmitter

Data Port (TXD)

These ports share the same address.

RXD is accessed during CPU read cycles. It is used to read

data from the Receiver Holding Register when the FIFOs

are disabled, or from the bottom of the RX_FIFO when the

FIFOs are enabled.

Receiver Data Port (RXD)

Bits 7-0 - Received Data

Used to access the Receiver Holding Register when the

FIFOs are disabled, or the bottom of the RX_FIFO when

the FIFOs are enabled.

TXD is accessed during CPU write cycles. It is used to write

data to the Transmitter Holding Register when the FIFOs

are disabled, or to the TX_FIFO when the FIFOs are en-

abled.

DMA cycles always access the TXD and RXD ports, regard-

less of the selected bank.

Transmitter Data Port (TXD)

Bits 7-0 - Transmitted Data

Used to access the Transmitter Holding Register when

the FIFOs are disabled or the top of TX_FIFO when the

FIFOs are enabled.

5.11.2

Interrupt Enable Register (IER)

This register controls the enabling of various interrupts.

Some interrupts are common to all operating modes of the

module, while others are mode specific. Bits 4 to 7 can be

set in Extended mode only. They are cleared in Non-Ex-

tended mode. The bits of the Interrupt Enable Register

(IER) are defined differently, depending on the operating

mode of the module.

The different modes can be divided into the following four

groups:

Non-Extended (which includes UART, Sharp-IR and

SIR).

UART and Sharp-IR in Extended mode.

SIR in Extended mode.

Consumer-IR.

The following sections describe the bits in this register for

each of these modes.

The reset mode for the IER is the Non-Extended UART

mode.

When edge-sensitive interrupt triggers are employed, user is

advised to clear all IER bits immediately upon entering the in-

terrupt service routine and to re-enable them prior to exiting

(or alternatively, to disable CPU interrupts and re-enable pri-

or to exiting). This will guarantee proper interrupt triggering in

the interrupt controller in case one or more interrupt events

occur during execution of the interrupt routine.

If the LSR, MSR or EIR registers are to be polled, interrupt

sources which are identified by self-clearing bits should

have their corresponding IER bits set to 0, to prevent spuri-

ous pulses on the interrupt output pin.

If an interrupt source must be disabled, the CPU can do so

by clearing the corresponding bit in the IER register. How-

ever, if an interrupt event occurs just before the correspond-

ing enable bit in the IER register is cleared, a spurious

interrupt may be generated. To avoid this problem, the

clearing of any IER bit should be done during execution of

the interrupt service routine. If the interrupt controller is pro-

grammed for level-sensitive interrupts, the clearing of IER

bits can also be performed outside the interrupt service rou-

tine, but with the CPU interrupt disabled.

Interrupt Enable Register (IER), in the Non-Extended

Modes (UART, SIR and Sharp-IR)

Upon reset, the IER supports UART, SIR and Sharp-IR in

the Non-Extended modes. See the bitmap of the Interrupt

Enable Register in these modes.

Bit 0 - Receiver High-Data-Level Interrupt Enable

(RXHDL_IE)

Setting this bit enables interrupts on Receiver High-

Data-Level, or RX_FIFO Time-Out events (EIR Bits 3-0

are 0100 or 1100. See Table 5-3 on page 110).

76543210

Reset

Required

Receiver Data

Port (RXD)

Bank 0,

Received Data

Offset 00h

76543210

Reset

Required

Transmitter Data

Port (TXD)

Bank 0,

Transmitted Data

Offset 00h

76543210

Reset

Required

MS_IE

Reserved

Interrupt Enable

RXHDL_IE

TXLDL_IE

LS_IE

Bank 0,

IER in Non-Extended Modes

Offset 01h

Reserved

PC87309VLJ Datasheet(PDF) 108 Page - National Semiconductor (TI)

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