PC87309VLJ datasheet(118/192 Pages) NSC

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Enhanced Serial Port with IR -UART2 (Logical Device 2)

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In addition, a fallback mechanism maintains this compatibil-

ity by forcing the UART to revert to 16550 mode if 16550

software addresses the module after a different mode was

set. Since setting the Baud Divisor values is a necessary ini-

tialization of the 16550, setting the divisor values in bank 1

forces the UART to enter 16550 mode. (This is called fall-

back.)

To enable other modes to program their desired baud rates

without activating this fallback mechanism, the Baud Gen-

erator Divisor Port pair in bank 2 should be used.

5.12.1

Legacy Baud Generator Divisor Ports (LBGD(L)

and LBGD(H)),

The programmable baud rates in the Non-Extended mode

are achieved by dividing a 24 MHz clock by a prescale value

of 13, 1.625 or 1. This prescale value is selected by the

PRESL field of EXCR2 (see page 121). This clock is subdi-

vided by the two Baud Generator Divisor buffers, which out-

put a clock at 16 times the desired baud (this clock is the

BOUT clock). This clock is used by I/O circuitry, and after a

last division by 16 produces the output baud.

Divisor values between 1 and 216-1 can be used. (Zero is

forbidden). The Baud Generator Divisor must be loaded

during initialization to ensure proper operation of the Baud

Generator. Upon loading either part of it, the Baud Genera-

tor counter is immediately loaded. Table 5-15 on page 120

shows typical baud divisors. After reset the divisor register

contents are indeterminate.

Any access to the LBGD(L) or LBGD(H) ports causes a re-

set to the default Non-Extended mode, i.e., 16550 mode

(See “AUTOMATIC FALLBACK TO A NON-EXTENDED

UART MODE” on page 107). To access a Baud Generator

Divisor when in the Extended mode, use the port pair in

bank 2 (BGD on page 119).

Table 5-12 shows the bits which are cleared when Fallback

occurs during Extended or Non-Extended modes.

If the UART is in Non-Extended mode and the LOCK bit is

1, the content of the divisor (BGD) ports will not be affected

and no other action is taken.

When programming the baud, the new divisor is loaded

upon writing into LBGD(L) and LBGD(H). After reset, the

contents of these registers are indeterminate.

Divisor values between 1 and 216-1 can be used. (Zero is

forbidden.) Table 5-14 shows typical baud divisors.

TABLE 5-12. Bits Cleared On Fallback

5.12.2

Link Control Register (LCR) and Bank Select

These registers are the same as the registers at offset 03h

in bank 0.

5.13 BANK 2 – EXTENDED CONTROL AND STATUS

REGISTERS

Bank 2 contains two alternate Baud Generator Divisor ports

and the Extended Control Registers (EXCR1 and EXCR2).

TABLE 5-13. Bank 2 Register Set

UART Mode & LOCK bit before Fallback

Extended

Mode

LOCK = x

Non-Extended

Mode

LOCK = 0

Non-Extended

Mode

LOCK = 1

MCR

2 to 7

none

EXCR1

0, 5 and 7

5 and 7

none

EXCR2

0 to 5

none

IRCR1

2 and 3

none

Offset

Name

Description

00h

BGD(L)

Baud Generator Divisor Port (Low

byte)

01h

BGD(H)

Baud Generator Divisor Port (High

byte)

02h

EXCR1

Extended Control Register 1

03h

LCR/BSR

Link Control/ Bank Select Register

04h

EXCR2

Extended Control Register 2

05h

Reserved

06h

TXFLV

TX_FIFO Level

07h

RXFLV

RX_FIFO Level

76543210

Reset

Required

Low Byte port

(LBGD(L))

Bank 1,

Least Significant Byte

Legacy Baud Generator Divisor

of Baud Generator

Offset 00h

76543210

Reset

Required

High Byte port

(LBGD(H))

Bank 1,

Most Significant Byte

Legacy Baud Generator Divisor

of Baud Generator

Offset 01h

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