PC87309VLJ datasheet(122/192 Pages) NSC

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Enhanced Serial Port with IR -UART2 (Logical Device 2)

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5.13.7

RX_FIFO Current Level Register (RXFLV)

This read-only register returns the number of bytes in the

RX_FIFO. It can be used for software debugging.

Bits 4-0 - Number of Bytes in RX_FIFO (RFL(4-0))

These bits specify the number of bytes in the RX_FIFO.

Bits 7-5 - Reserved

Read/Write 0.

Note: The contents of TXFLV and RXFLV are not frozen

during CPU reads. Therefore, invalid data could be re-

turned if the CPU reads these registers during normal

transmitter and receiver operation. To obtain correct da-

ta, the software should perform three consecutive reads

and then take the data from the second read, if first and

second read yield the same result, or from the third

read, if first and second read yield different results.

5.14 BANK 3 – MODULE REVISION ID AND SHADOW

REGISTERS

Bank 3 contains the Module Revision ID register which

identifies the revision of the module, shadow registers for

monitoring various registers whose contents are modified

by being read, and status and control registers for handling

the flow control.

TABLE 5-17. Bank 3 Register Set

5.14.1

Module Revision ID Register (MRID)

This read-only register identifies the revision of the module.

When read, it returns the module ID and revision level. This

module returns the code 2xh, where x indicates the revision

number.

Bits 3-0 - Revision ID (MID3-0)

The value in these bits identifies the revision level.

Bits 7-4 - Module ID (MID7-4)

The value in these bits identifies the module type.

5.14.2

Shadow of Link Control Register (SH_LCR)

This register returns the value of the LCR register. The LCR

5-9 on page 114, is written to the LCR/BSR registers loca-

tion (at offset 03h) from any bank.

See “Link Control Register (LCR)” on page 112 for bit de-

scriptions.

Offset

Name

Description

00h

MRID

Module Revision ID Register

01h

SH_LCR

Shadow of LCR Register

(Read Only)

02h

SH_FCR

Shadow of FIFO Control Register

(Read Only)

03h

LCR/

BSR

Link Control Register/

Bank Select Register

04h-07h

Reserved

76543210

Reset

Required

RX_FIFO Current Level

Bank 2,

RFL2

RFL4

RFL0

RFL1

RFL3

Extended Modes

Offset 07h

Reserved

76543210

Reset

Required

Module Revision ID

(MRID)

Bank 3,

Offset 00h

Revision ID(RID 3-0)

Module ID(MID 7-4)

76543210

Reset

Required

Link Control Register

(SH_LCR)

Bank 3,

Shadow of

STB

EPS

STKP

SBRK

BKSE

WLS0

WLS1

PEN

Offset 01h

PC87309VLJ Datasheet(PDF) 122 Page - National Semiconductor (TI)

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