Obsolete

Product(s)

- Obsolete

Product(s)

L6995S

18/26

6.5 Output voltage setting

To select the output divider network there isn't a specific criteria, but a low divider network value (around 100

Ω)

reduces the efficiency at low current; instead a high value divider network (500K

Ω) increase the noise effects.

A network divider values from 1K to 50K is right. From the Eq4:

R10 = 1K

Ω

R9 = 390

Ω

The device output voltage is adjustable by connecting a voltage divider from output to VSENSE pin. Minimum

tain the required output voltage and switching frequency, the following equation gives the smallest input voltage,

Eq 25

6.6 Voltage Feed Forward

Choosing the switching frequency around 270KHz from the Eq1. It can be selected the input divider. For exam-

ple:

R3=560K

Ω

R4=28K

Ω

In order to compensate the comparator delay R4 resistor should be increased around 20%.

R4=33K

Ω

6.7 Current limit resistor

must be considered the temperature effect. So two STS25NH3LL have 2.75m

Ω @ 25°C, at 100°C can be con-

sidered 3.85m

Ω.

R8 = 47K

Ω

6.8 Integrator capacitor

Since VREF = 0.9V, from Eq4, it follows

is lower than 150mV the system doesn't need the second integrator capacitor.

6.9 Soft start capacitor

Considering the soft start equations (Eq. 11) at page 10, it can be found:

These equations are valid whitout load. When an active load is present the equantions result more complex;

further some active loads have unexpected effect, as higher current than the expected one during the start up,

that can change the start up time.

In this case the capacitor value can be selected on the application; anyway the Eq11 gives an idea about the

δ 1

α

OSC

α

OUT

---------------

1

K

OSC

T

OFFMIN

------------------------







------------------------------

⋅

–

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