AS6C2016 datasheet(6/13 Pages) ALSC

No. de pieza	AS6C2016

Descripción Electrónicos	Fully static operation

PDF	13 Pages

Scroll/Zoom	100%

Fabricante Electrónico	ALSC [Alliance Semiconductor Corporation]

Página de inicio	https://www.alliancememory.com

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TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

Dout

Data Valid

tOH

tAA

Address

tRC

Previous Data Valid

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

Dout

Data Valid

High-Z

tCLZ

tOLZ

tCHZ

tOHZ

tOH

OE#

tOE

LB#,UB#

tBHZ

tACE

CE#

tAA

Address

tRC

tBA

tBLZ

Notes :

1.WE#is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.

3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.

4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

128K X 16 BIT LOW POWER CMOS SRAM

FEBRUARY 2008

AS6C2016

FEBRUARY/2008, V 1.c

Alliance Memory Inc.

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