ICS93722 datasheet(1/6 Pages) ICST

No. de pieza	ICS93722

Descripción Electrónicos	Low Cost DDR Phase Lock Loop Zero Delay Buffer

PDF	6 Pages

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Fabricante Electrónico	ICST [Integrated Circuit Systems]

Página de inicio	http://www.icst.com

Logo

1 / 6 page

Integrated

Circuit

Systems, Inc.

ICS93722

0539E—07/18/03

Block Diagram

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Pin Configuration

28-Pin SSOP

Recommended Application:

DDR Zero Delay Clock Buffer

Product Description/Features:

•

Low skew, low jitter PLL clock driver

•I

2C for functional and output control

•

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

•

3.3V tolerant CLK_INT input

Switching Characteristics:

•

PEAK - PEAK jitter (66MHz): <120ps

•

PEAK - PEAK jitter (>100MHz): <75ps

•

CYCLE - CYCLE jitter (66MHz):<110ps

•

CYCLE - CYCLE jitter (>100MHz):<65ps

•

OUTPUT - OUTPUT skew: <100ps

•

Output Rise and Fall Time: 650ps - 950ps

•

DUTY CYCLE: 49.5% - 50.5%

Functionality

FB_INT

CLK_INT

SCLK

SDATA

Control

Logic

FB_OUTT

CLKT0

CLKT1

CLKT2

CLKT3

CLKT4

CLKT5

CLKC0

CLKC1

CLKC2

CLKC3

CLKC4

CLKC5

PLL

S

T

U

P

N

IS

T

U

P

T

U

O

e

t

a

t

S

L

P

D

V

AT

N

I

_

K

L

CT

K

L

CC

K

L

CT

T

U

O

_

B

F

V

5

.

2

)

m

o

n

(

LL

H

L

n

o

V

5

.

2

)

m

o

n

(

HH

L

H

n

o

V

5

.

2

)

m

o

n

(

z

H

M

0

2

<Z

Z

f

o

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

SCLK

CLK_INT

N/C

VDDA

GND

VDD

CLKT2

CLKC2

GND

CLKC5

CLKT5

CLKC4

CLKT4

VDD

SDATA

N/C

FB_INT

FB_OUTT

N/C

CLKT3

CLKC3

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

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