TNETX3150A datasheet(45/78 Pages) TI

45 / 78 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Figure 12 shows the various register spaces provided by and accessed through the TNETX15AE.

Address High

DIO

MII I/F

EEPROM I/F

SRAM I/F

Address Low

Data

Auto- Increment

SIO

RAM Addr

RAM Data

SRAM

(External)

Serial EEPROM

MII/PHYs

TNETX15AE

Access Registers

Internal

DIO Registers

Figure 12. Register Spaces Provided and Accessed Through the TNETX15AE

DIO interface

The DIO interface is asynchronous to allow easy adaptation to a range of microprocessor devices and computer

system

interfaces.

The

DIO

interface

designed

operate

from

the

same

bus

the

TNETX3150/TNETX3150A/TNETX3100 DIO interface. Thus, both devices are accessed using the same DIO

read and write routines. Each device is selected for DIO reads and writes through independent chip-select

signals. Chip select for the TNETX3150/TNETX3150A/TNETX3100 is named SCS, while chip select for the

TNETX15AE

named

ESCS.

Figure

shows

how

the

TNETX15AE

and

the

TNETX3150/TNETX3150A/TNETX3100 share the DIO interface.

Microprocessor

TNETX3150/TNETX3150A/

TNETX3100

EINT

TNETX15AE

SDATA7–SDATA0

SAD1–SAD0

SRNW

SRDY

ESCS

SCS

Figure 13. DIO Interface Bus

TNETX3150A Datasheet(PDF) 45 Page - Texas Instruments

TNETX3150A Datasheet(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Descarga

Enlace URL