LAN91C100FD datasheet(54/79 Pages) SMSC

No. de pieza	LAN91C100FD

Descripción Electrónicos	FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

PDF	79 Pages

Scroll/Zoom	100%

Fabricante Electrónico	SMSC [SMSC Corporation]

Página de inicio	http://www.smsc.com

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54 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 54

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE

significant bits.

RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the

value until read low is used to determine completion. When an EEPROM access is in progress the

STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C100FD

can be read or written until the EEPROM operation completes and both bits are clear.

This

mechanism is also valid for reset initiated reloads.

Note:

If no EEPROM is connected to the LAN91C100FD, for example for some embedded applications, the

ENEEP pin should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base,

and Individual Address assume their default values upon hardware reset and the CPU is responsible for

programming them for their final value.

LAN91C100FD Datasheet(PDF) 54 Page - SMSC Corporation