CLC408 datasheet(7/12 Pages) NSC

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Capacitance across Rf

Do not place a capacitor across Rf

Use a resistor with low parasitic

capacitance for Rf

A capacitive load

Use a series resistor between the output

and a capacitive load (see the

Settling

Time vs. CL plot)

Long traces and/or lead lengths between Rf

and the CLC408

Keep these traces as short as possible

For non-inverting and transimpedance gain configurations:

Extra capacitance between the inverting

pin and ground (Cg)

See the

Printed Circuit Board Layout

sub-section below for suggestions on

reducing Cg

Increase Rf if peaking is still observed

after reducing Cg

For inverting gain configurations:

Inadequate ground plane at the non-inverting

pin and/or long traces between non-inverting

pin and ground

Place a 50 to 200

Ω resistor between the

non-inverting pin and ground (see Rt in

Figure 2)

Capacitive Loads

Capacitive loads, such as found in A/D converters,

require a series resistor (Rs) in the output to improve

settling performance. The

Settling Time vs. Capacitive

Load plot in the Typical Performance Characteristics

section provides the information for selecting this resistor.

Using a resistor in series with a reactive load will also

reduce the load’s effect on amplifier loop dynamics.

For instance, driving coaxial cables without an output

series resistor may cause peaking or oscillation.

Transmission Line Matching

One method for matching the characteristic impedance

of a transmission line is to place the appropriate

resistor at the input or output of the amplifier. Figure 6

shows the typical circuit configurations for matching

transmission lines.

Figure 6: Transmission Line Matching

In non-inverting gain applications, Rg is connected

directly to ground. The resistors R1, R2, R6, and R7 are

equal to the characteristic impedance, Zo, of the trans-

mission line or cable. Use R3 to isolate the amplifier

from reactive loading caused by the transmission line,

or by parasitics.

In inverting gain applications, R3 is connected directly to

ground. The resistors R4, R6, and R7 are equal to Zo.

The parallel combination of R5 and Rg is also equal to Zo.

The input and output matching resistors attenuate the

signal by a factor of 2, therefore additional gain is needed.

Use C6 to match the output transmission line over a greater

frequency range. It compensates for the increase of

the op amps output impedance with frequency.

Thermal Design

To calculate the power dissipation for the CLC408,

follow these steps:

1) Calculate the no-load op amp power:

Pamp = ICC • (VCC – VEE)

2) Calculate the output stage’s RMS power:

Po = (VCC – Vload) • Iload , where Vload and Iload

are the RMS voltage and current across the

external load

3) Calculate the total op amp RMS power:

Pt = Pamp + Po

To calculate the maximum allowable ambient tempera-

ture, solve the following equation: Tamb = 175 – Pt •

JA, where θJA is the thermal resistance from junction

to ambient in °C/W, and Tamb is in °C. The Package

Thermal Resistance section contains the thermal

resistance for various packages.

Dynamic Range (input /output protection)

ESD diodes are present on all connected pins for pro-

tection from static voltage damage. For a signal that

may exceed the supply voltages, we recommend using

diode clamps at the amplifier’s input to limit the signals

to less than the supply voltages.

The CLC408’s output current can exceed the maximum

safe output current. To limit the output current to <

96mA:

Limit the output voltage swing with diode

clamps at the input

Make sure that

Vo(max) is the output voltage swing limit, and Io(max) is

the maximum safe output current.

Dynamic Range (input /output levels)

The

Electrical Characteristics section specifies the

Common-Mode Input Range and Output Voltage

Range; these voltage ranges scale with the supplies.

Output Current is also specified in the

Electrical

Characteristics section.

V2 +-

CLC408

o(max)

≥

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