AD9480

Rev. A | Page 6 of 28

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted.

Table 4.

AD9480-250

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CLOCK

Maximum Conversion Rate

Full

VI

250

MSPS

Minimum Conversion Rate

Full

VI

20

MSPS

Full

IV

1.2

2

ns

Full

IV

1.2

2

ns

OUTPUT PARAMETERS

Full

VI

1.9

ns

Full

VI

2.8

3.8

ns

Full

V

0.5

ns

Full

V

0.5

ns

Full

VI

1.9

2.7

3.7

ns

Full

IV

0

0.1

0.6

ns

Pipeline Latency

25°C

VI

8

Cycles

APERTURE

25°C

V

1.5

ns

Aperture Uncertainty (Jitter)

25°C

V

0.25

ps rms

TIMING DIAGRAM

N–1

N

N+1

N+8

N+9

N+10

N+11

N–8

8 CYCLES

N–7

N

N+1

N+2

CLK+

CLK–

DATA

OUT

DCO–

DCO+

AIN

Figure 2. Timing Diagram