COP8782C datasheet(3/28 Pages) NSC

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COP8780CCOP8781CCOP8782C

Absolute Maximum Ratings

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Supply Voltage (VCC)7V

Programming Voltage VPP (RESET pin)

and ME (pin G6)

134V

Voltage at any Pin

03V to VCC a 03V

Total Current into VCC Pin (Source)

50 mA

Total Current out of GND Pin (Sink)

60 mA

Storage Temperature Range

65 Cto a150 C

Note

Absolute maximum ratings indicate limits beyond

which damage to the device may occur DC and AC electri-

cal specifications are not ensured when operating the de-

vice at absolute maximum ratings

DC Electrical Characteristics COP87XXC b40 C s TA s a85 C unless otherwise specified

Parameter

Condition

Min

Typ

Max

Units

Operating Voltage

Power Supply Ripple (Note 1)

Peak to Peak

01 VCC

Supply Current

CKI e 10 MHz (Note 2)

VCC e 6V tc e 1 ms21

HALT Current (Note 3)

VCC e 6V CKI e 0 MHz

Input Levels

RESET CKI

Logic High

09 VCC

Logic Low

01 VCC

All Other Inputs

Logic High

07 VCC

Logic Low

02 VCC

Hi-Z Input Leakage

VCC e 60V

Input Pullup Current

VCC e 60V VIN e 0V

250

G Port Input Hysteresis

(Note 6)

005 VCC

Output Current Levels

D Outputs

Source

VCC e 45V VOH e 38V

Sink

VCC e 45V VOL e 10V

All Others

Source (Weak Pull-Up)

VCC e 45V VOH e 32V

110

Source (Push-Pull Mode)

VCC e 45V VOH e 38V

Sink (Push-Pull Mode)

VCC e 45V VOL e 04V

TRI-STATE Leakage

Allowable SinkSource

Current per Pin

D Outputs (Sink)

All Others

3mA

Maximum Input Current (Notes 4 6)

Room Temp

200

without Latchup (Room Temp)

RAM Retention Voltage Vr

(Note 5)

Input Capacitance

(Note 6)

Load Capacitance on D2

(Note 6)

1000

Note 1

Rate of voltage change must be less than 05Vms

Note 2

Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open

Note 3

The HALT mode will stop CKI from oscillating in the RC and the crystal configurations Halt test conditions All Inputs tied to VCC L C and G port IO’s

configured as outputs and programmed low D outputs programmed low the window for UV erasable packages is completely covered with an opaque cover to

prevent light from falling onto the die during HALT mode test Parameter refers to HALT mode entered via setting bit 7 of the G Port data register

Note 4

Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will

have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective

resistance to VCC is 750X (typ) These two pins will not latch up The voltage at the pins must be limited to less than 14V

Note 5

To maintain RAM integrity the voltage must not be dropped or raised instantaneously

Note 6

Parameter characterized but not tested

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