MP7610

7

Rev. 4.01

A3

A2

A1

A0

D13

D12

D11

D10

D9

D8

D0

1

0

SDI

(Data In)

CLK

LD

SDO

Previous Data

DAC Register

Loaded

A3 (1)

1

0

1

0

1

0

Figure 1. Serial Data Timing and Loading

Figure 2. Serial Data Input Timing (RST = “1”)

Figure 3. Reset Operation

1

0

SDI

SDO

CLK

LD

HIGH Z

+2 LSB Band

1

0

1

0

1

0

+FS

--FS

Note:

(1) CLK should be high during the falling edge of LD to insure proper function of the shift register.

RST

1

0

Note:

(1) Because A3 is available immediately after 18th clock edge of DATA Shift-in, only 17 clock cycles are

needed to complete the readback.

MSB