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AD7694

Data Sheet

APPLICATION INFORMATION

SW+

MSB

16,384C

IN+

LSB

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

REF

GND

IN–

32,768C

SW–

MSB

16,384C

LSB

32,768C

Figure 18. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7694 is a low power, single-supply, 16-bit ADC using a

successive approximation architecture. It is capable of con-

verting 250,000 samples per second (250 kSPS) and powers

down between conversions. When operating at 100 SPS, for

example, it typically consumes 4 µW, ideal for battery-powered

applications.

The AD7694 provides the user with on-chip, track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiple, multiplexed channel applications.

The AD7694 is specified from 2.7 V to 5.25 V. It is housed in an

8-lead MSOP. The AD7694 is an improved second source to

LTC1864 and LTC1864L. For even better performance, the

AD7685 should be considered.

CONVERTER OPERATION

The AD7694 is a successive approximation ADC based on a

charge redistribution DAC. Figure 18 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to GND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on the IN+ and IN− inputs. When the

acquisition phase is complete and the CNV input goes high, a

conversion phase begins. When the conversion phase begins,

SW+ and SW− are opened first. The two capacitor arrays are

then disconnected from the inputs and connected to the GND

input. Thus, the differential voltage between the inputs, IN+

and IN−, captured at the end of the acquisition phase applies to

the comparator inputs, causing the comparator to become

unbalanced. By switching each element of the capacitor array

between GND and REF, the comparator input varies by binary

weighted voltage steps (VREF/2, VREF/4 … VREF/65536). The

control logic toggles these switches, starting with the MSB, in

order to bring the comparator back into a balanced condition.

After the completion of this process, the part returns to the

acquisition phase and the control logic generates the ADC

output code.

Because the AD7694 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

TRANSFER FUNCTIONS

The ideal transfer function for the AD7694 is shown in

Figure 19 and Table 8.

000...000

000...001

000...010

111...101

111...110

111...111

ANALOG INPUT

+FS – 1.5 LSB

FS – 1 LSB

–FS + 1 LSB

–FS

–FS + 0.5 LSB

Figure 19. ADC Ideal Transfer Function

Table 8. Output Codes and Ideal Input Voltages

Description

Analog Input

VREF = 5 V

Digital Output Code

Hexadecimal

FSR – 1 LSB

4.999924 V

FFFF1

Midscale + 1 LSB

2.500076 V

8001

Midscale

2.5 V

8000

Midscale – 1 LSB

2.499924 V

7FFF

–FSR + 1 LSB

76.3 µV

0001

–FSR

0 V

00002

This is also the code for an overranged analog input (VIN+ – VIN– above

VREF – VGND).

This is also the code for an underranged analog input (VIN+ – VIN– below VGND).

Rev. B | Page 12 of 16

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