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SL28647 Datasheet(PDF) 10 Page - Silicon Laboratories

No. de pieza SL28647
Descripción Electrónicos  Clock Generator for Intel짰CK505
PDF  27 Pages
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Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL28647 Datasheet(HTML) 10 Page - Silicon Laboratories

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SL28647
.....................Document #: 001-05103 Rev *B Page 10 of 27
0
HW
PWRGOOD
Power on reset status bit
0 = All of the below conditions are not meet
1 = Valid voltage levels exist on VDD_SRC/CPU, VDD_REF, VDDA,
VDD_48, VDD_PCI and CKPWRGD is asserted and external crystal is
detected.
Byte 12 Control Register 12
Bit
@Pup
Name
Description
Byte 13 Control Register 13
Bit
@Pup
Name
Description
7
0
CLKREQ#9
CLKREQ#9 Input Enable
0 = Disabled, 1 = Enabled
6
0
CLKREQ#8
CLKREQ#8 Input Enable
0 = Disabled, 1 = Enabled
5
0
CLKREQ#7
CLKREQ#7 Input Enable
0 = Disabled, 1 = Enabled
4
0
CLKREQ#6
CLKREQ#6 Input Enable
0 = Disabled, 1 = Enabled
3
0
CLKREQ#5
CLKREQ#5 Input Enable
0 = Disabled, 1 = Enabled
2
0
CLKREQ#4
CLKREQ#4 Input Enable
0 = Disabled, 1 = Enabled
1
0
CLKREQ#3
CLKREQ#3 Input Enable
0 = Disabled, 1 = Enabled
0
0
CLKREQ#2
CLKREQ#2 Input Enable
0 = Disabled, 1 = Enabled
Byte 14 Control Register 14
Bit
@Pup
Name
Description
7
0
CLKREQ#1
CLKREQ#1 Input Enable
0 = Disabled, 1 = Enabled
6
1
LCD _96/100M Clock
Speed
LCD 96_100M Clock Speed
0 = 96 MHz, 1 = 100 MHz
5
1
27M_SS Bit 0
27M SS Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
4
1
27M_non-SS Bit 0
27M non-SS Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
3
1
PCI4 Bit 0
PCI4 Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
2
1
PCI3 Bit 0
PCI3 Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
1
1
PCI2 Bit 0
PCI2 Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
0
1
PCI1 Bit 0
PCI1Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = Highh
Byte 15 Control Register 15
Bit
@Pup
Name
Description
7
HW
TME_STRAP
Trusted mode enable strap status,
0 = Normal
1 = No overclocking (default)
6
1
RESERVED
RESERVED
5
1
RESERVED
RESERVED



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