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5220-DS02-R Datasheet(PDF) 30 Page - Broadcom Corporation.

No. de pieza 5220-DS02-R
Descripción Electrónicos  10/100BASE-TX/FX Mini Transceiver
PDF  90 Pages
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Fabricante Electrónico  BOARDCOM [Broadcom Corporation.]
Página de inicio  http://www.broadcom.com
Logo BOARDCOM - Broadcom Corporation.

5220-DS02-R Datasheet(HTML) 30 Page - Broadcom Corporation.

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BCM5220
Preliminary Data Sheet
04/20/04
Broa d c om Co rp o r a t i o n
Page 18
Media Independent Interface (MII) Management Interface: Register Programming
Document
5220-DS04-405-R
Sec t i on 5: Re gi st er Su mm a r y
MEDIA INDEPENDENT INTERFACE (MII) MANAGEMENT INTERFACE:
REGISTER PROGRAMMING
The BCM5220 fully complies with the IEEE 802.3u Media Independent Interface (MII) specification. The MII management
interface registers are serially written to and read from using the MDIO and MDC pins. A single clock waveform must be
provided to the BCM5220 at a rate of 0–25MHz through the MDC pin. The serial data is communicated on the MDIO pin.
Every MDIO bit must have the same period as the MDC clock. The MDIO bits are latched on the rising edge of the MDC
clock.
See Table 6 for the fields in every MII instruction’s read or write packet frame.
Preamble (PRE)
32 consecutive 1 bits must be sent through the MDIO pin to the BCM5220 to signal the beginning of an MII instruction. Fewer
than 32 1 bits causes the remainder of the instruction to be ignored, unless the Preamble Suppression mode is enabled
(register 01, bit 6).
Start of Frame (ST)
A 01 pattern indicates that the start of the instruction follows.
Operation Code (OP)
A read instruction is indicated by 10, while a write instruction is indicated by 01.
PHY Address (PHYAD)
A 5-bit PHY address follows next, with the MSB transmitted first. The PHY address allows a single MDIO bus to access
multiple transceivers. The BCM5220 supports the full 32-PHY address space.
Register Address (REGAD)
A 5-bit register address follows, with the MSB transmitted first. The register map of the BCM5220, containing register
addresses and bit definitions, are provided on the following pages.
Table 6: MII Management Frame Format
Operation
PRE
ST
OP
PHYAD
REGAD
TA
DATA
Idle
Direction
READ
1 ... 1
01
10
AAAAA
RRRRR
ZZ
Z0
Z ... Z
D ... D
Z
Z
Driven to BCM5220
Driven by BCM5220
WRITE
1 ... 1
01
01
AAAAA
RRRRR
10
D ... D
Z
Driven to BCM5220



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