MPM3630

– SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR

MPM3630 Rev. 1.0

www.MonolithicPower.com

12

6/21/2016

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current. The optimized internal compensation

network minimizes the external component

counts and simplifies the control loop design.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MPM3630 UVLO comparator monitors the

output voltage of the internal regulator (VCC).

The UVLO rising threshold is about 4.1V while

its falling threshold is 3.36V.

ENABLE/SYNC Control (EN)

EN turns the converter on and off. Drive EN

high to turn on the converter; drive EN low to

turn off the converter. An internal 1.1

MΩ

resistor from EN to GND allows EN to be

floated to shut down the chip.

EN is clamped internally using a 5.6V series-

Zener-diode (see Figure 4).

1.1MΩ

5.6

Figure 4: 5.6V Zener Diode Connection

Connecting EN to a voltage source directly

without a pull-up resistor requires limiting the

amplitude of the voltage source to

≤ 5V to

prevent damage to the Zener diode.

Connecting the EN input through a pull-up

resistor to the voltage on VIN limits the EN input

current to less than 100µA.

For external clock synchronization, connect a

clock with a frequency range between 1MHz

and 2MHz. 2.2ms after the output voltage is set,

the internal clock rising edge will synchronize

with the external clock rising edge. Meanwhile

the width of the high level should be longer than

250ns, and the width of the low level should be

longer than 100ns.

Internal Soft Start (SS)

The soft start prevents the converter output

voltage from overshooting during startup. When

the chip starts, the internal circuitry generates a

soft-start voltage (SS) that ramps up from 0V to

5V. When SS is lower than REF, the error

amplifier uses SS as the reference. When SS is

higher than REF, the error amplifier uses REF

as the reference. The SS time is set to 2.2ms

internally.

Power Good Indicator (PG)

The MPM3630 has power good (PG) output to

indicate whether the output voltage of the

module is ready. PG is an open-drain output.

Connect PG to VCC (or another voltage source)

through a pull-up resistor (e.g. 10 k

Ω). When

the input voltage is applied, PG is pulled down

pulled high (after a 110

μs delay). During

normal operation, PG is pulled low when the

μs

delay).

Since

the

MPM3630

doesn’t

implement

dedicated output over-voltage protection, PG

will not respond to an output over-voltage

condition.

Over-Current Protection (OCP) and Hiccup

The MPM3630 has a cycle-by-cycle over-

current limiting control. When the inductor

current peak value exceeds the internal peak

current limit threshold, the HS-FET turns off and

the LS-FET turns on, remaining on until the

inductor current falls below the internal valley

current limit threshold. The valley current limit

circuit is employed to decrease the operation

frequency (after the peak current limit threshold

is triggered). Meanwhile, the output voltage

threshold

(240mV,

typically).

Once

UV

is

triggered, the MPM3630 enters hiccup mode to

re-start the part periodically. This protection

mode is useful when the output is dead-shorted

to ground and greatly reduces the average

short-circuit current to alleviate thermal issues

and protect the converter. The MPM3630 exits

hiccup mode once the over-current condition is

removed.

Thermal Shutdown (TSD)

Thermal shutdown prevents the chip from

operating at exceedingly high temperatures.

When the silicon die reaches temperatures that

exceed 150°C, it shuts down the whole chip.