TSS901EASLASH883 datasheet(9/31 Pages) ATMEL

9 / 31 page

TSS901E

Rev. C – 24-Aug-01

TSS901E channel 2 status and control registers

CH1_CNTRL1

channel 1 control Register 1

r / w

CH1_CNTRL2

channel 1 control Register 2

r / w

CH1_HTID

channel 1 Header Transaction ID byte

CH1_HCNTRL

channel 1 Header control byte

CH1_ESR1

channel 1 detailed error source register 1

r / w

CH1_ESR2

channel 1 detailed error source register 2

r / w

reserved

---

CH1_COMICFG

channel 1 COMI configuration register

r / w

CH1_TX_SAR

channel 1 transmit Start Address Register

0000

r / w

CH1_TX_EAR

channel 1 transmit End Address Register

0000

r / w

CH1_TX_CAR

channel 1 transmit Current Address Register

0000

CH1_TX_FIFO

channel 1 transmit FIFO

CH1_TX_EOPB

channel 1 transmit EOP Bit Register

CH1_RX_SAR

channel 1 receive Start Address Register

0000

r / w

CH1_RX_EAR

channel 1 receive End Address Register

0000

r / w

CH1_RX_CAR

channel 1 receive Current Address Register

0000

CH1_RX_FIFO

channel 1 receive FIFO

xxxxxxxx

CH1_STAR

channel 1 Status Register

Port Width / Address

(hex)

Function

Reset Value

(hex)

Access

Port Width / Address

(hex)

Function

Reset Value

(hex)

Access

CH2_DSM_MODR

channel 2 DSM mode Register

r / w

CH2_DSM_CMDR

channel 2 DSM command Register

r / w

CH2_DSM_STAR

channel 2 DSM status Register

r / w

CH2_DSM_TSTR

channel 2 DSM test Register

r / w

CH2_ADDR

channel 2 address Register

r / w

CH2_RT_ADDR

channel 2 Route Address Register

r / w

TSS901EA/883 Datasheet(PDF) 9 Page - ATMEL Corporation

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