TSS901EASLASH883 datasheet(15/31 Pages) ATMEL

No. de pieza	TSS901EA/883

Descripción Electrónicos	Tripple Point to Point IEEE 1355 High Speed Controller

PDF	31 Pages

Scroll/Zoom	100%

Fabricante Electrónico	ATMEL [ATMEL Corporation]

Página de inicio	http://www.atmel.com

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15 / 31 page

TSS901E

Rev. C – 24-Aug-01

TCK

Test Clock. Provides an asynchronous clock for JTAG boundary

scan.

TMS

Test Mode Select. Used to control the test state machine.

TDI

Test Data Input. Provides serial data for the boundary scan

logic.

TDO

O/Z

Test Data Output. Serial scan output of the boundary scan

path.

350

RESET*

TSS901E Reset. Sets the TSS901E to a known state. This

input must be asserted (low) at power-up. The minimum width

of RESET low is 5 cycles of CLK10 in parallel with CLK

running.

CLK

External clock input to TSS901E (max. 25 Mhz).

Must be derived from RAM access time.

CLK10

External clock input to TSS901E DS-links (application specific,

nominal 10 Mhz). Used to generate to transmission speed and

link disconnect timeout.

PLLOUT

Output of internal PLL. Used to connect a network of external

RC devices.

VCC

Power Supply

GND

Ground

Signal Name

Type

Function

max. output

current [mA]

load [pF]

tCKH

tCKL

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