ADC12DL066 datasheet(3/23 Pages) NSC

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Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

INA+

INB+

Differential analog input pins. With a 1.0V reference voltage

the differential full-scale input signal level is 2.0 V

P-P with

each input pin voltage centered on a common mode voltage,

CM. The negative input pins may be connected to VCM for

single-ended operation, but a differential input signal is

required for best performance.

INA−

INB−

REF

Reference input. This pin should be bypassed to AGND with

a 0.1 µF capacitor when an external reference is used. V

REF

is 1.0V nominal and should be between 0.8V to 1.5V.

INT/EXT REF

Reference source select pin. With a logic low at this pin the

internal 1.0V reference is selected and the V

REF pin need

not be driven. With a logic high on this pin an external

reference voltage should be applied to V

REF input pin 7.

RPA

RPB

These pins are high impedance reference bypass pins.

Bypass per Section 1.2. DO NOT LOAD these pins.

RMA

RMB

RNA

RNB

DIGITAL I/O

CLK

Digital clock input. The range of frequencies for this input is

as specified in the electrical tables with guaranteed

performance at 66 MHz. The input is sampled on the rising

edge of this input.

OEA

OEB

OEA and OEB are the output enable pins that, when low,

holds their respective data output pins in the active state.

When either of these pins is high, the corresponding outputs

are in a high impedance state.

PD is the Power Down input pin. When high, this input puts

the converter into the power down mode. When this pin is

low, the converter is in the active mode.

Output Format pin. A logic low on this pin causes output

data to be in offset binary format. A logic high on this pin

causes the output data to be in 2’s complement format.

ADC12DL066 Datasheet(PDF) 3 Page - National Semiconductor (TI)

ADC12DL066 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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