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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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DAC5686IPZP Datasheet(PDF) 33 Page - Texas Instruments |
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DAC5686IPZP Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 46 page  www.ti.com f NCO + freq F DAC 232 Register Bit Allocation Map REGISTER DESCRIPTIONS DAC5686 SLWS147B – APRIL 2003 – REVISED AUGUST 2004 The NCO accumulator is reset to zero when the PHSTR pin is high and remains at zero until PHSTR is set low. Frequency word freq in the frequency register is added to the accumulator every clock cycle. The output frequency of the NCO is: While the maximum clock frequency of the DACs is 500 MSPS, the maximum clock frequency the NCO can operate at is 320 MHz; mixing at DAC rates higher than 320 MSPS requires using the fs/4 mixing option. NAME R/W AD- BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DRESS chip_ver R/W 0x00 atest[4:0] version[2:0] read only freq_lsb R/W 0x01 freq_int[7:0] freq_lmidsb R/W 0x02 freq_int[15:8] freq_umidsb R/W 0x03 freq_int[23:16] freq_msb R/W 0x04 freq_int[31:24] phase_lsb R/W 0x05 phase_int[7:0] phase_msb R/W 0x06 phase_int[15:8] config_lsb R/W 0x07 mode[1:0] div[1:0] sel[1:0] counter fbypass config_msb R/W 0x08 ssb interl sinc dith sync_phstr nco sif4 twos config_usb R/W 0x09 dual clk dds_gain[1:0] rspect qflag pll_rng[1:0] rev_bbus daca_offset_lsb R/W 0x0A daca_offset[7:0] daca_gain_lsb R/W 0x0B daca_gain[7:0] daca_offset_gain_ R/W 0x0C daca_offset[10:8] sleepA daca_gain[11:8] msb dacb_offset_lsb R/W 0x0D dacb_offset[7:0] dacb_gain_lsb R/W 0x0E dacb_gain[7:0] dacb_offset_gain_ R/W 0x0F dacb_offset[10:8] sleepB dacb_gain[11:8] msb Register Name: chip_ver MSB LSB atest[4:0] chip_ver[2:0] read only 0 0 0 0 0 1 0 1 chip_ver[3:0]: chip_ver [3:0] stores the device version, initially 0x5. The user can find out which version of the DAC5686 is in the system by reading this byte. a_test[4:0]: must be 0 for proper operation. Register Name: freq_lsb MSB LSB freq_int[7:0] 0 0 0 0 0 0 0 0 33 |
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