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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AM652X Datasheet(PDF) 217 Page - Texas Instruments |
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AM652X Datasheet(HTML) 217 Page - Texas Instruments |
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217 / 299 page  OSPI_DQS OSPI_D[i:0] OSPI_TIMING_06 O21 O 2 2 OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 217 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 Figure 5-96. OSPI Timing Requirements - SDR, No Loopback Clock and Internal Pad Loopback Clock Figure 5-97. OSPI Timing Requirements - SDR, External Loopback Clock Table 5-91. OSPI DLL Delay Mapping for Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BITFIELD DELAY VALUE 1.8V, OSPI0 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x45 1.8V, OSPI1 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x4B 3.3V, OSPI0 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x46 3.3V, OSPI1 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x4C 1.8V, OSPI0 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x14 1.8V, OSPI1 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x16 3.3V, OSPI0 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3A 3.3V, OSPI1 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3E All other modes PHY_CONFIG_TX_DLL_DELAY_FLD, PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 5.11.5.19 OLDI Table 5-92. OLDI Switching Characteristics NO. PARAMETER MODE MIN MAX UNIT O1 LVDS Low-to-High Transition Time max IOSET1 0.18 0.5 ns O2 LVDS high-to-low Transition Time max IOSET1 0.18 0.5 ns O3 Transmitter Output Bit Width Min IOSET1 1 1 UI O4 Transmitter Pulse Positions – Normalized IOSET1 0.25 0.75 ns O5 Variation in transmitter pulse position across Bit 7:0 pulse positions IOSET1 -0.06 0.06 ns O6 TxOut Channel to Channel Skew IOSET1 110 ns O7 Transmitter Jitter Cycle-to-Cycle IOSET1 0.028 0.035 ns O8 Input Total Jitter Tolerance (Includes data to clock skew, pulse position variation.) IOSET1 0.25 ns |
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