NET2890 datasheet(29/73 Pages) ETC

29 / 73 page

Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

4.6.2 OUT FIFOs

When receiving data, the NET2890 will NAK the host (indicating that it cannot accept the data) if either the

FIFO runs out of room, or the Data Packet Received Interrupt status bit is set. USB OUT transfers can

overlap with the local CPU unloading the data using the following sequence:

•

When the local CPU gets the Data Packet Received Interrupt, it reads the FIFOCNT register so it

knows how many bytes are in the current packet.

•

Then the local CPU clears the Data Packet Received Interrupt which allows the next packet to be

received.

•

Now the local CPU can unload data from the FIFO while the next USB OUT transaction is occurring.

4.7 Interrupt and Status Register Operation

4.7.1 Interrupt Status Register 1 (IRQSTAT1)

Bits 4:0 of this register indicate whether one of the endpoints has an interrupt pending. These bits cannot be

written, and can cause a local interrupt if the corresponding interrupt enable bits are set in the IRQENB1

a 1. This bit can cause a local interrupt if the corresponding interrupt enable bit is set in the IRQENB1

set. This allows the local CPU to operate in a polled, as well as an interrupt driven environment.

4.7.2 Interrupt Status Register 2 (IRQSTAT2)

Each of the bits of this register is set when a particular event occurs in the NET2890, and are cleared by

writing a 1 to the corresponding bit. These bits can cause a local interrupt if the corresponding interrupt

enable bits are set in the IRQENB2 register.

4.7.3 Endpoint Response Registers (EPRSPSET, EPRSTCLR)

Each endpoint has a set of Endpoint Response Registers. The bits in these registers determine how the

NET2890 will respond to various situations during a USB transaction. Writing a 1 to any of the bits in the

EPRSPSET register will set the corresponding bits. Writing a 1 to any of the bits in the EPRSPCLR

4.7.4 Endpoint Interrupt Status Register (EPIRQSTAT)

Each endpoint has an Endpoint Interrupt Status Register. Each of the bits of this register is set when a

particular endpoint event occurs, and are cleared by writing a 1 to the corresponding bit. These bits can

cause a local interrupt if the corresponding interrupt enable bits are set in the EPIRQENB register. Reading

the EPRIQSTAT register returns the current state of the bits.

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