NET2890 datasheet(14/73 Pages) ETC

14 / 73 page

Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

3. Pin Description

Pin Type

Description

Input

OOutput

I/O

Bi-Directional

Schmitt Trigger

Tri-State

Totem-Pole

Open-Drain

50K Pull-Down

50K Pull-Up

Active low

NOTE: Input pins that do not have an internal pull-up or pull-down resistor (designated by PU or PD in the

”Type” column below) must be driven externally when the NET2890 is in the suspended state.

Signal Name

Type

Description

CLKIN

48 MHz Oscillator input. Connect to 48 MHz crystal.

CLKOUT

48 MHz Oscillator output. Connect to 48 MHz crystal. The oscillator

stops when the device is suspended by the USB Host.

RESET#

I, S, PU

Reset. External reset. Connect to local or power-on reset. To reset

when oscillator is stopped (initial power-up or in suspend state), assert

for at least two ms. When oscillator is running, assert for at least five

48-MHz clock periods.

DP,DM

3,4

I/O

USB Data Port

DP and DM are the differential data signals of the USB data port

NOTE: An external 1.5 K

Ω resistor must be connected from DP to

3.3V. This pull-up resistor indicates to the host or upstream hub that a

full-speed device is connected to the USB.

D[7:0]

5-11,

I/O, 12mA,

Data Bus. The bi-directional 8-bit data bus is used by devices on the

local bus to read or write registers or FIFOs in the NET2890. D7 is the

most-significant bit.

A[4:0]

42-38

Address Bus. The local address bus is used by devices on the local

bus to select registers within the NET2890. A4 is the most-significant

bit.

CS#

I, PU

Chip Select. The chip select is used by devices on the local bus to

enable access to registers within the NET2890. This signal is ignored

if DACK# is asserted.

IOR#

I, PU

I/O Read. The I/O read strobe is asserted along with CS# and A[4:0]

when a device on the local bus reads from an internal register or FIFO.

It also allows a FIFO to be read during DMA transfers when DACK#

is asserted.

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