AD5544BCPZ-R2 datasheet(4/24 Pages) AD

4 / 24 page

AD5544/AD5554

Data Sheet

Rev. H | Page 4 of 24

SPECIFICATIONS

AD5544 ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VSS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, VREFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature

range of −40°C to +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Test Condition/Comments

Min

Typ

Max

Unit

STATIC PERFORMANCE1

Resolution

1 LSB = V

REFx/2

16 = 153 µV when V

REF = 10 V

Bits

Relative Accuracy

INL

AD5544BRSZ

±1

LSB

AD5544ARSZ

±2

LSB

AD5544BCPZ

±1

LSB

AD5544ACPZ-1

±4

LSB

Differential Nonlinearity

DNL

AD5544BRSZ

±1

LSB

AD5544ARSZ

±1.5

LSB

AD5544BCPZ

±1

LSB

AD5544ACPZ-1

±1

LSB

Output Leakage Current

OUTx

Data = 0x0000, T

A = 25°C

Data = 0x0000, T

A = 85°C

Full-Scale Gain Error

FSE

Data = 0xFFFF

±0.75

±3

Full-Scale Tempco2

TCV

ppm/°C

Feedback Resistor

FBx

DD = 5 V

kΩ

REFERENCE INPUT

REFx Range

REFx

−15

+15

Input Resistance

REFx

kΩ

Input Resistance Match

REFx

Channel-to-channel

0.35

Input Capacitance2

REFx

ANALOG OUTPUT

Output Current

OUTx

Data = 0xFFFF

1.25

2.5

Output Capacitance2

OUTx

Code dependent

LOGIC INPUT AND OUTPUT

Logic Input Low Voltage

0.8

Logic Input High Voltage

2.4

Input Leakage Current

µA

Input Capacitance2

Logic Output Low Voltage

OL = 1.6 mA

0.4

Logic Output High Voltage

OH = 100 µA

INTERFACE TIMING2, 3

Clock Width High

Clock Width Low

CS to Clock Setup

CSS

Clock to CS Hold

CSH

Clock to SDO Propagation

Delay

Load DAC Pulse Width

LDAC

Data Setup

Data Hold

Load Setup

LDS

Load Hold

LDH

SUPPLY CHARACTERISTICS

Power Supply Range

DD RANGE

2.7

5.5

Positive Supply Current

Logic inputs = 0 V

µA

Negative Supply Current

Logic inputs = 0 V, V

SS = −5 V

0.001

µA

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