AT24C02 datasheet(5/13 Pages) HOTCHIP

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SERIAL 2K（256×8）EEPROM

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AT24C02(C)

Data Valid (D)

The state of the data line represents valid data

when, after a Start condition, the data line is stable

for the duration of the high period of the clock

signal.

The data on the line must be changed during

the low period of the clock signal. There is one

clock pulse per bit of data.

Each data transfer is initiated with a Start

condition and terminated with a Stop condition.

The number of data bytes transferred between

Start and Stop conditions is determined by the

master device and is, theoretically, unlimited

(although only the last sixteen will be stored when

doing a write operation). When an over write does

occur, it will replace data in a first-in first-out (FIFO)

fashion.

Acknowledge

Each receiving device, when addressed, is

obliged to generate an acknowledge after the

reception of each byte. The master device must

generate an extra clock pulse which is associated

with this Acknowledge bit.

Note: The 24C02 does not generate any

Acknowledge bits if an internal programming

cycle is in progress.

e device that acknowledges has to pull

down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is stable low

during the high period of the acknowledge related

clock pulse.

Of course, setup and hold times

must be taken into account. During reads, a master

must signal an end of data to the slave by not

generating an Acknowledge bit on the last byte that

has been clocked out of the slave. In this case, the

slave (24C02) will leave the data line high to enable

the master to generate the Stop condition

FIGURE 7-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Device Addressing

A control byte is the first byte received

following the Start condition from the master device.

The control byte consists of a four-bit control code.

For the 24C02, this is set as ‘1010’binary for read

and write operations. The next three bites of the

control byte are “don’t cares” for the 24C02.

The last bit of the control byte defines the

operation to be performed. When set to’1’, a read

operation is selected. When set to ‘0’, a write

operation is selected. Following the start condition,

the 24C02 monitors the SDA bus, checking the

device type identifier being transmitted and, upon

a ‘1010’code, the slave device outputs an

Acknowledge signal on the SDA line. Depending

on the state of the select a read or write operation

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