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HM3412 Datasheet(PDF) 8 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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HM3412 Datasheet(HTML) 8 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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8 / 10 page ![]() converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. The output ripple is determined by: ) C F 8 1 ESR ( I V OUT OSC COUT L OUT Where FOSC = operating frequency, COUT= output capacitance and ΔIL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Two 22μF ceramic capacitors are recommended value in typical application. Inductor Selection For high efficiencies, the inductor should have a low DC resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a higher impact on efficiency. When using small chip inductor, the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. A reasonable starting point for setting ripple current, ΔL, is 40% of maximum output current. The recommended inductor value can be calculated as below: L SW MAX , IN OUT OUT I F V / V 1 V L L MAX , OUT MAX , L I 2 / 1 I I To avoid the saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current. Layout Consideration The layout design of HM3412 regulator is relatively simple. For the best efficiency and minimum noise problems, we should place the following components close to the IC: CIN, L, RH and RL: 1) Multi-layer board is suggested for HM3412 output current application. It is desirable to maximize the PCB copper area connecting to GND pin to achieve the best thermal and noise performance. Reasonable vias are suggested to be placed around GND pins to enhance the soldering quality and thermal performance. 2) CIN must be close to Pins IN and GND. The loop area formed by CIN and GND must be minimized. 3) The PCB copper area associated with SW pin must be minimized to avoid the potential noise problem. 4) The components RH and RL, and the trace connecting to the FB pin must not be adjacent to the SW net on the PCB layout to avoid the noise problem. 6V 6.0A 1.2MHz Synchronous Step-Down Regulator |
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