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STR720 Datasheet(PDF) 393 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 393 Page - STMicroelectronics |
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393 / 401 page  STR720 - ELECTRICAL CHARACTERISTICS 393/401 28.11.2.3 Integral non-linearity (INL) This parameter expresses the deviation between the actual A/D convertion characteristics and the ideal one by evaluating the distance between the center of the actual convertion step and the center of the bisector line, which is obtained by drawing a straight line from 1/2 LSB before the first step of real characteristic to 1/2 LSB after its last step. 28.11.2.4 Differential non-linearity (DNL) This parameter again expresses the deviation between actual and ideal A/D convertion characteristics. This time the size of actual step with respect to the ideal one (1 ideal LSB) is compared. 28.11.2.5 Total harmonic distortion (THD) The FFT computed on the acquired samples is processed so to calculated the ratio between the power of input sine wave fundamental component and the power of all other harmonic components. 28.11.2.6 Pass-band ripple (PBR) This parameter defines the characteristics of A/D converter transfer function from analog input pin to the generated sample values. 28.12 External Memory Bus Timing The signal composing the external memory interface are collected on Port 7 and as such all their DC electrical characteristics are reported in Table 99. The following tables and figures report the timing characteristics of read and write cycles. Table 108. EMI Read cycle timing characteristics Symbol Parameter(1) Test Conditions(2), (3) Value(4) Unit Min Typ Max tRPR1 Read pulse time for ERD in 8/16-bit word access Depends on EMI configu- ration.(5) 2TC - x 9TC + x ns tRPC1 Read pulse time for ECSx in 8/ 16-bit word access Depends on EMI configu- ration.(5) 2TC - x 9TC + x ns tRPR2 Read pulse time for ERD in 32-bit word access Depends on EMI configu- ration.(5) 4TC - x 18TC + x ns tRPC2 Read pulse time for ECSx in 32-bit word access Depends on EMI configu- ration.(5) 4TC - x 18TC + x ns tRSP Read sampling point TC - x TC + x ns tRDS Read data setup time ns tRDH Read data hold time ns tRASR Read address setup time to ERD TC - x TC + x ns tRASC Read address setup time to ECSx TC - x TC + x ns tRAH Read address hold time ns |
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