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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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STR720 Datasheet(PDF) 397 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 397 Page - STMicroelectronics |
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397 / 401 page  STR720 - ELECTRICAL CHARACTERISTICS 397/401 1. See Figure 85, Figure 86 and Figure 87 for a definition of these parameters. 2. VDD(all) = 1.80 V ± 10%, VDD3(all) = 3.30 V ± 10%, TA = -40 / +85 °C unless otherwise specified. 3. Data based on design guidelines, not tested in production. 4. TC is CPU clock period expressed in ns. For example if CPU clock is set to run at 50 MHz, TC =20 ns. 5. Actual duration is configurable. See Chapter 10: DRAM CONTROLLER (DRAMC) on page 101. In the following figures the timing diagrams are represented, where also the extent of the software configurable access timing is depicted. tSCADA SDRAM CAS to data valid delay (CAS latency)(3) Depends on SDRAM config- uration.(5) TC -3TC ns tSPRD SDRAM precharge delay(3) Depends on SDRAM config- uration.(5) 0- 7TC ns Figure 85. SDRAM Single Read Access Table 110. SDRAM Read cycle timing characteristics Symbol Parameter(1) Test Conditions(2) Value(4) Unit Min Typ Max delay RAS-CAS latency CAS tSCH MICLK MIA[13:11] Bank MIA[10:0] Row Col MCS[x] MISA / RAS MIAA / CAS MID[32:0] Data MIWE delay precharge tSCL tSCAD tSCCS tSCRA tSCCA tSCWE tSDS tSDH Activate Bank Read Precharge Bank Note: this diagram shows the timing with RAS-CAS delay, CAS latency and precharge delay all set to 1 wait-state. |
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