XRT85L61

BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR

REV. 1.0.1

3

PIN DESCRIPTIONS

1

MCLK1

I

Reference T1 Clock input:

This signal is an independent 1544 kHz clock with accuracy better than

+ 32 ppm and duty cycle within 40% to 60%. This clock provides timing

source for the PLL clock recovery circuit in T1 mode.

to operate.

2

JAEN

I

Jitter Attenuator Enable:

Tie this pin “High” to enable the Jitter Attenuator. When enabled, a 32 bit

FIFO is included in the data path for all modes of operation.

Ω resistor

3

MCLK2

I

Reference E1 and 64 kHz Clock Input:

This signal is an independent 2048 kHz clock with accuracy better than +

50 ppm and duty cycle within 40% to 60%. This clock provides timing

source for the PLL clock recovery circuit in E1 and 64 kHz mode.

To reduce intrinsic jitter when the JA is enabled, it is

recommended to have a reference clock with an accuracy of ±

25 ppm or better. If E1 mode or 64 kHz mode is not used, this

clock is not necessary for the device to operate.

4

JAVDD

***

VDD for Jitter Attenuator (3.3V ± 5%)

5

JAGND

***

Jitter Attenuator Ground

6

ICT

I

In circuit Testing

When this pin is grounded, all output pins are Tri-stated for testing pur-

poses.

Ω resistor

7

RTIP

I

Receive Positive Input

8

RRING

I

Receive Negative Input

9

AVDD

***

Analog VDD (3.3V ± 5%)

10

AGND

***

Analog Ground