AD9546SLASHPCBZ datasheet(126/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 126 of 205

Table 80. Maximum DPLL Loop Filter Bandwidth

NCO Gain Filter

Bandwidth

Selection

LF0 Maximum

Loop Bandwidth

(Hz)

LF1 Maximum

Loop Bandwidth

(Hz)

1850

305

925

152.5

462.5

76.3

231.3

38.1

115.6

19.1

57.81

9.53

28.91

4.77

14.45

2.38

7.227

1.191

3.613

0.596

1.807

0.298

0.9033

0.149

0.4517

0.745

0.2258

0.037

0.1219

0.019

0.0565

0.009

DPLL NCO

The DPLL NCO requires an external clock source. In the case

of the AD9546, the external clock source drives the XOA and

XOB input pins, from which an integrated PLL synthesizer

generates a clock signal that is approximately 2.4 GHz.

The DPLL normally operates in closed-loop fashion (that is, as

a PLL), which is the normal operating mode, wherein the loop

filter is the FTW source for the NCO. However, under certain

conditions, the DPLL operates in an open-loop configuration.

Figure 91 differentiates between the two configurations by

means of a switch. A loop controller determines whether the

DPLL is in closed-loop operation (switch closed) or open-loop

operation (switch open), while an FTW processor determines

the FTW source for the NCO.

DIGITAL

PHASE

DETECTOR

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

FTW

PROCESSOR

LOOP

CONTROLLER

XOA XOB

AD9546

TDC

48-BIT

FTW

FREERUN

TUNING WORD

DIGITAL CROSS

POINT MUX

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0

N DIVIDER

REG 0x1005 TO 0x1000,

BITS[45:0]

Figure 91. DPLL Block Diagram

Figure 91 also shows the lock detectors (see the DPLL Lock

Detectors section). For details on the feedback divider, see the

DPLL Feedback Divider (N Divider) section. For clarity, Figure 91

also shows the digital cross point mux and TDCs that feed the

digital phase detector. The TDCs convert the rising edges of the

input and feedback signals to numeric time stamps (see the

Time to Digital Converter (TDC) section for details).

Although Figure 91 shows the N divider connected directly to

the NCO output, this diagram is a simplification of the actual

feedback path (see Figure 82 in the Frequency Translation

Loops section). However, regarding the operation and control

of the DPLL, this simplification is valid in the context of the

following paragraphs.

Frequency tuning of the DPLL is by virtue of an NCO, which

employs a sigma-delta modulator (SDM) architecture. The

SDM has an internal integer divider that divides down the

system clock frequency with the output of the divider

constituting the output of the NCO. The SDM effectively

modulates the modulus of this divider to produce an output

frequency that is a fractionally scaled down version of the

system clock frequency based on an input 48-bit FTW. Because

the NCO is SDM-based, it employs noise shaping that

redistributes its modulation noise away from the NCO output

frequency (the APLL, which follows the DPLL, suppresses the

out of band modulation noise of the SDM).

The output frequency of the NCO (fNCO) depends primarily on

the numeric value of the 48-bit FTW and the frequency of the

system clock (fS) per the following equation:

fNCO = fS × FTW/248

For a given fS and a desired fNCO, compute FTW as

FTW = round(248 × fNCO/fS)

(18)

where round(x) is a function to round x to the nearest integer.

The NCO automatically converts the 48-bit FTW into two

components: an integer part (INT) and a fractional part

(FRAC). INT and FRAC relate to FTW as

INT = floor(248/FTW)

(19)

FRAC = 2−40 × round(240 × ((248/FTW) − INT))

(20)

where:

7 ≤ INT ≤ 13.

0.05 ≤ FRAC ≤ 0.95.

floor(x) is a function that leaves x unchanged if x is an integer.

Otherwise, x becomes the nearest integer in the negative

direction.

The constraints on INT and FRAC necessarily impose

limitations on the choice of FTW. For example, let fS =

2.30 GHz and fNCO = 245.76 MHz, which yields (per

Equation 18).

FTW = 30,076,213,163,657

Then, per Equation 19 and Equation 20,

INT = 9

FRAC = 0.35872395833303016843274235725403

In this case, INT and FRAC satisfy their defined constraints.

Although the preceding example validates FTW for the given fS

and fNCO, the example does not necessarily validate FTW for a

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