AD9546SLASHPCBZ datasheet(127/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 127 of 205

given application. That is, the preceding example assumes fS

and fNCO are completely static values. However, fS is only as

stable as the oscillator or resonator at the XOA and XOB pins.

Furthermore, with the DPLL locked to an input reference

signal, fNCO tracks variations in the reference frequency.

Therefore, the user must assess variations on FTW for a given

application. That is, the user must consider upper and lower

FTW values, which lead to upper and lower INT and FRAC

values as well.

For example, assume in the preceding example that input

frequency variations cause the FTW to vary by 0.5%, leading to

two FTW values that differ from 30,076,213,163,657 by 0.5%:

Lower FTW = 29,925,832,097,839

Upper FTW = 30,226,594,229,475

The upper and lower FTW values lead to the following INT and

FRAC values:

INTUPPER = 9

FRACUPPER = 0.3121631426201929571107029914856

INTLOWER = 9

FRACLOWER = 0.40575272194291756022721529006958

In this case, the upper and lower INT values and upper and

lower FRAC values satisfy the constraints on INT and FRAC.

The upper and lower INT values must be the same. Otherwise,

having different values implies that the upper and lower FTW

values cross an SDM integer boundary, which can lead to poor

spurious performance. There are two ways to remedy this

problem. The first, which is less workable, is to limit the

variation on the system clock frequency and the reference input

frequency. The second is to choose a new FTW value (and, by

implication, a new fNCO value). In either case, the goal is to

constrain the variation of the FTW such that the FTW yields

identical (and valid) upper and lower INT values, as well as

valid upper and lower FRAC values.

The NCO applies adjustments to INT and FRAC as necessary

when the system clock compensation feature is active (see the

System Clock Compensation section).

NCO GAIN TUNING WORD FILTER BANDWIDTH

Although not explicitly shown in Figure 91, the NCO contains

a digital low-pass filter, the NCO gain tuning word filter. This

filter has a single-pole response similar to a simple resistor and

capacitor low-pass filter (see Figure 92), but with a variable gain

component that compensates for the nonlinear gain of the

NCO. The NCO gain tuning word filter reduces frequency

transients that can occur when the DPLL switches between

closed-loop and open-loop operating modes (active to

holdover, for example).

TUNING

WORD

TIME

FTW2

FTW1

INPUT

OUTPUT

TRANSITION

TIME

Figure 92. NCO Gain Tuning Word Filter Response

To control the filter bandwidth, use Bits[3:0] (unsigned integer)

in Register 0x1009 for DPLL0 and Register 0x1409 for DPLL1.

Table 81 shows how the value of Bits[3:0] relates to the

bandwidth and resulting transition time.

To prevent degradation of the phase margin associated with the

DPLL loop filter (see the DPLL Loop Filter section), the user

must be careful to choose an NCO gain tuning word filter

bandwidth from Table 81 that is at least 100 times greater than

the loop bandwidth of the DPLL. This value includes any

expansion of the DPLL loop filter bandwidth by the fast

acquisition block, if enabled (see the DPLL Fast Acquisition

Options section).

Table 81. NCO Gain Tuning Word Filter Bandwidth Selections

Bits[3:0]

3 dB Bandwidth (Hz)

Transition Time (ms)

248,000

0.003

124,000

0.006

62,000

0.013

31,000

0.026

15,500

0.051

7800

0.102

3900

0.204

1900

0.419

970

0.820

490

1.62

240

3.32

120

6.63

13.0

26.5

53.1

7.6

105

The NCO gain tuning word filter has implications when using

the NCO as a traditional, open-loop digital frequency synthesizer.

For example, when the DPLL is programmed for freerun mode

(see the Freerun Tuning Word section), the DPLL operates like

a traditional NCO. That is, the user can program different

freerun tuning words to synthesize different frequencies. In a

traditional NCO, programming a new tuning word results in an

instantaneous switch from the initial frequency to the new

frequency (like the input trace shown in Figure 92). However,

AD9546/PCBZ Datasheet(PDF) 127 Page - Analog Devices

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