AD9546SLASHPCBZ datasheet(128/205 Pages) AD

128 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 128 of 205

in the case of the DPLL, when programming different tuning

words, the NCO transitions from one frequency to the next

smoothly based on the programmed bandwidth of the NCO

gain tuning word filter, as shown in Figure 92 (see Table 81 for

the transition time to 99% of a step input).

DPLL LOCK DETECTORS

DPLL Phase Lock Detector

Each DPLL channel (DPLL0 and DPLL1) contains a completely

digital phase lock detector. The user controls the threshold

sensitivity and hysteresis of the phase lock detector via the

source profiles (see the Source Profiles section).

The phase lock detector indicates the phase lock status via Bit 1

of Register 0x3100 for DPLL0 and Register 0x3200 for DPLL1

(Logic 0 is unlocked and Logic 1 is locked). However, because

Bit 1 is dynamic in nature, the recommendation is to use the

interrupt request (IRQ) mechanism for phase lock indication

instead. The IRQ mechanism observes the state of Bit 1 and

latches the state transitions. Specifically, Bit 0 of Register

0x3010 for DPLL0 and Register 0x3015 for DPLL1 latches a

status change from phase unlocked to phase locked as a Logic 1.

Likewise, Bit 1 of the same registers latches a status change

from phase locked to phase unlocked as a Logic 1. Because Bit 0

and Bit 1 are latched bits, however, they may represent a

condition that is no longer true. Therefore, the user must clear

the phase locked and phase unlocked status via Bit 0 and Bit 1,

respectively, of Register 0x200B for DPLL0 and Register 0x2010

for DPLL1. Otherwise, the user may lose indication of

subsequent state transitions by the phase lock detector (see the

Interrupt Request (IRQ) section).

The phase lock detector behaves in a manner analogous to

water in a tub (see Figure 93). The total capacity of the tub

is 4096 units, with −2048 denoting empty, 0 denoting the 50%

point, and +2047 denoting full. The tub also has a safeguard to

prevent overflow. Furthermore, the tub has a low water mark

at −1025 and a high water mark at +1024. To change the water

level, the phase lock detector adds water with a fill bucket or

removes water with a drain bucket.

The user specifies the size of the fill and drain buckets via the

source profiles. To specify the phase lock fill rate, use Bits[7:0]

(unsigned integer) of the appropriate source profile at the start

address shown in Table 78 plus an offset of 3 (decimal). To

specify the phase lock drain rate use Bits[7:0] of the appropriate

source profile at the start address shown in Table 78 plus an offset

of 4 (decimal).

The water level in the tub is what the lock detector uses to

determine the lock and unlock conditions. When the water

level is below the low water mark (−1025), the lock detector

indicates an unlock condition. Conversely, when the water level

is above the high water mark (1024), the lock detector indicates a

lock condition. When the water level is between the marks, the lock

detector holds its previous condition. Figure 93 shows this

concept with an overlay of an example of the instantaneous

water level (vertical) vs. time (horizontal) and the resulting

lock/unlock states.

2047

–2048

1024

–1025

LOCK LEVEL

UNLOCK LEVEL

LOCKED

UNLOCKED

STATE

RATE

DRAIN RATE

Figure 93. Lock Detector Diagram

The user has access to the 12-bit (signed) instantaneous water

level value of the phase lock detector via Register 0x3109 to

(DPLL1). As shown in Figure 93, the pertinent water level

values appear along the left side of the tub.

During any given PFD phase error sample, the lock detector

either adds water with the fill bucket or removes water with the

drain bucket (one or the other, but not both). The decision of

whether to add or remove water depends on the phase lock

threshold level specified by the user via Bits[23:0] (unsigned

integer) of the appropriate source profile at the start address

shown in Table 78 plus an offset of 0 to 2 (decimal). The value

of Bits[23:0] is the desired threshold in picoseconds. Thus, the

phase lock threshold extends from 0 ps to 16.7 µs and

represents the phase error at the output of the PFD. Though the

programming range supports 0 ps as a lower limit, in practice,

the minimum value must be greater than 50 ps.

The phase lock detector compares the absolute value of each

phase error sample at the output of the PFD to the programmed

phase threshold value. If the absolute value of the phase error

sample is less than or equal to the programmed phase threshold

value, the detector control logic adds one fill bucket into the

tub. Otherwise, the detector control logic removes one drain

bucket from the tub. The magnitude of the phase error sample

(polarity is ignored), relative to the phase threshold value,

determines whether to fill or drain the bucket.

Regarding the fill and drain process, an exception to normal

operation occurs when the phase slew limiter is active. When

the phase slew limiter is actively in the limiting process, the lock

detector inhibits fill events, allowing only drain events to occur.

When more filling is taking place than draining, the water level

in the tub eventually rises above the high water mark (1024),

which causes the lock detector to indicate lock. When more

draining is taking place than filling, the water level in the tub

eventually falls below the low water mark (−1024), which

causes the lock detector to indicate unlock. The ability to

specify the threshold level, fill rate, and drain rate enables the

user to tailor the operation of the lock detector to the statistics

of the timing jitter associated with the input reference signal.

Note that, for debug purposes, the user can make the fill or

drain rate zero to force the lock detector to indicate a lock or

unlock state, respectively.

AD9546/PCBZ Datasheet(PDF) 128 Page - Analog Devices

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