AD9546SLASHPCBZ datasheet(133/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 133 of 205

TUNING WORD OFFSET CLAMP

The DPLL contains a frequency clamp that places bounds on

the frequency range of the DPLL output. The frequency clamp

feature (see Figure 95) is beneficial for applications in which

downstream devices cannot tolerate frequencies beyond

prescribed limits.

The clamp feature uses Bits[23:0] (unsigned) in Register 0x1006

to Register 0x1008 (for DPLL0) and Register 0x1406 to

clamp value. The frequency clamp feature is always active.

However, the default value of the frequency clamp is the

maximum clamp value, which establishes a default frequency

clamp limit of approximately ±586 kHz (for a system clock

frequency of 2.4 GHz). Given a 320 MHz NCO output

frequency, a 586 kHz frequency clamp equates to an offset of

approximately 1800 ppm (or 0.18%).

The frequency offset, fCLAMP, defines an upper and lower

frequency bound as a deviation from the frequency given by the

freerun tuning word of the DPLL. The relationship between

fCLAMP, the system clock frequency (fS), and the frequency clamp

value is as follows:

fCLAMP = Frequency clamp value × (fS/236)

For example, given a system clock frequency of 2.4 GHz and a

desired frequency offset clamp limit of ±10 kHz (that is,

fS = 2.4 × 109 and fCLAMP = 104), find the frequency clamp value.

Solving the fCLAMP equation for the frequency clamp value,

Frequency clamp value = 236 × fCLAMP/fS

(22)

= 236 × 104/(2.4 × 109)

= 286,331 (nearest integer)

= 0x 04 5E7B (hexadecimal)

In some cases, it is more useful to specify fCLAMP as a fractional

offset of the NCO output frequency (in percent or parts per

million, for example).

For example, given a system clock frequency of 2.4 GHz, an

NCO output frequency of 250 MHz and a desired frequency

offset clamp limit of 25 ppm (25 × 10−6), find the frequency

clamp value. First, determine fCLAMP as follows:

fCLAMP = 25 × 10−6 × 250 MHz

= 6250 Hz

Next, substitute fCLAMP into Equation 22.

Frequency Clamp Value = 236 × fCLAMP/fS

= 236 × 6250/(2.4 × 109)

= 178,957 (nearest integer)

= 0x 02 BB0D (hexadecimal)

When the frequency clamping circuitry is actively clamping the

frequency, status Bit 1 is Logic 1 in Register 0x3102 (for DPLL0)

and Register 0x3202 (for DPLL1). Bit 1 relates to the IRQ

function (see the Interrupt Request (IRQ) section) through

Bit 6 and Bit 7 (frequency clamp active and inactive, respectively)

in Register 0x3010 (for DPLL0) and Register 0x3015 (for

DPLL2). Because Bit 6 and Bit 7 are latched, the user must use

Bit 6 and Bit 7, respectively, of Register 0x200B (for DPLL0)

and Register 0x2010 (for DPLL1) to clear the latched state.

Otherwise, the user cannot observe subsequent state transitions

of Bit 1.

DIGITAL

PHASE

DETECTOR

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

FTW

PROCESSOR

LOOP

CONTROLLER

XOA XOB

AD9546

TDC

48-BIT

FTW

FREERUN TUNING WORD

DIGITAL CROSS

POINT MUX

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0

N DIVIDER

REG 0x1005 TO 0x1000, BITS[45:0]

REG 0x1008 TO 0x1006, BITS[23:0]

Figure 95. Tuning Word Offset Clamp Feature

AD9546/PCBZ Datasheet(PDF) 133 Page - Analog Devices

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