AD9546SLASHPCBZ datasheet(135/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 135 of 205

TUNING WORD HISTORY

The DPLLs have a tuning word processor that handles the

application of tuning words to the NCO. The tuning word

processor embodies several of the functional blocks shown in

Figure 91, including the loop controller, FTW processor, and

the switch. The NCO can receive tuning words from the

following three possible sources:

•

Freerun tuning word

•

Digital loop filter

•

Tuning word averaging processor

This section focuses on the tuning word averaging processor,

which provides the following three digital outputs residing in

the register map:

•

DPLL tuning word history

•

DPLL history available status

•

DPLL history updated status

The DPLL tuning word history is a 46-bit unsigned value that

resides in Register 0x3103 to Register 0x3108 (for DPLL0) and

The DPLL history available status is available via Bit 0 of

The DPLL history updated status is available via Bit 2 of

The user also has access to the DPLL history available status

and DPLL history updated status as a physical logic level via an

appropriately configured Mx pin.

The main purpose of the averaging processor is to compute an

average of tuning word samples when a DPLL translation profile

initially becomes active (but after expiration of any delays specified

by the delay element of the averaging processor as detailed the

Averaging Processor Delay section). After the averaging processor

collects enough samples to allow a valid tuning word average

computation, the processor sets the DPLL history available

status bit to Logic 1, indicating that the averaged tuning word

history is available. If the DPLL needs to switch to holdover

operation, the DPLL can use the averaged tuning word history

of the averaging processor. Otherwise, the DPLL uses the last

available tuning word from the loop filter or the value in the DPLL

freerun tuning word, depending on the configuration of the

averaging processor.

The averaging processor comprises the following three

functional elements:

•

Delay

•

Windowed average

•

Continue or reset

These functional elements respond to user input via the register

map, as explained in the Averaging Processor Delay section, the

Averaging Processor Windowed Average section, and the

Averaging Processor Continue or Reset section.

Averaging Processor Delay

By default, as soon as a translation profile becomes active (see the

Reference Switching section for what constitutes an active

translation profile), the tuning word processor resets the averaging

processor (and DPLL history available status bit) and the averaging

processor immediately starts processing tuning words from the

loop filter.

However, the user has access to two independent mechanisms to

impose a delay between when a translation profile becomes

active and when the averaging processor begins the tuning

word averaging process: an event dependent delay and a timed

delay.

By default, both mechanisms are inactive, implying no delay.

Event dependent delays take priority over time delays: first, any

of the three possible event dependent delay selections

programmed by the user, then the timed delay programmed by

the user. Until these delays expire, the tuning word processor

ignores incoming tuning words.

The status of the DPLL is the basis for the event dependent

delay mechanism. To invoke the event dependent delay, write a

Logic 1 to any combination of the following delay history

control bits:

•

DPLL delay history until phase lock

•

DPLL delay history until frequency lock

•

DPLL delay history until not slew limiting

These bits reside in Bits[5:3] of Register 0x100E (for DPLL0)

and Register 0x140E (for DPLL1). Logic 1 invokes the

described delay. The DPLL delay history until phase lock bit

(Bit 3) causes the averaging process to delay until the DPLL

phase locks. The DPLL delay history until frequency lock bit

(Bit 4) causes the averaging process to delay until the DPLL

frequency locks. The DPLL delay until not slew limiting bit (Bit

5) causes the averaging process to delay until the phase slew

limiter ceases slew limiting, assuming slew limiting occurs (see

the Phase Slew Rate Limit section).

When more than one of the delay history control bits are Logic 1,

the implementation of the delay behaves as an AND function of

the selected conditions. That is, all the selected status

conditions must be satisfied before the averaging process

begins. The status conditions are real-time status indicators as

they follow the actual state of the DPLL. However, the moment

all selected status conditions are true, the averaging processor

waits for the prescribed holdoff period to expire (assuming the

DPLL history holdoff time is not zero) and starts the averaging

process (even if any of the status conditions become false after

the averaging processor starts averaging).

AD9546/PCBZ Datasheet(PDF) 135 Page - Analog Devices

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