AD9546SLASHPCBZ datasheet(136/205 Pages) AD

136 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 136 of 205

The user specifies the desired delay, or holdoff period, Bits[7:0]

(unsigned) in Register 0x1010 (for DPLL0) and Register 0x1410

(for DPLL1). A value of zero implies no delay. Bits[7:0]

constitute the DPLL history holdoff time. The delay relates to

the DPLL history holdoff time value as follows:

Delay = DPLL History Holdoff Time × (tACCUM/8)

where tACCUM is the time specified by the DPLL history

accumulation timer value (see the Averaging Processor

Windowed Average section for details on the DPLL history

accumulation timer).

The delay (if enabled) is also in effect following a pause/restart

trigger event (see the Averaging Processor Continue or Reset

section).

Averaging Processor Windowed Average

DPLL History Accumulation Timer

In general, the averaging processor collects tuning word

samples generated by the loop filter and computes an average

of the tuning word samples. The user specifies an averaging

window for the rolling average time span via Bits[27:0]

(unsigned) of Register 0x100A to Register 0x100D (for DPLL0)

and Register 0x140A to Register 0x140D (for DPLL1).

Bits[27:0] constitute the DPLL history accumulation timer value.

The units associated with Bits[27:0] are milliseconds allowing

averaging time spans from 0.001 sec to 268,435.455 sec

(~74.5 hours). The default value is 10 (decimal), yielding a

default averaging window time span of 10 ms.

The time span of the averaging window relates to the value of

the DPLL history accumulation timer as follows:

Time Span = DPLL History Accumulation Timer × 10−3

The recommended minimum averaging window time span is at

least 10 times the minimum expected period of the signal at the

input to the phase/frequency detector of the DPLL.

As an example, determine the value of the DPLL history

accumulation timer necessary to provide a 15-minute

windowed average. First, solve the time span equation for the

DPLL history accumulation timer as follows:

DPLL History Accumulation Timer = Time Span × 1000

= (15 × 60) × 1000

= 900,000

= 0x 00D BBA0 (hexadecimal)

DPLL history accumulation timer = 0 is a special case. This

value bypasses the averaging processor by routing tuning word

samples from the digital loop filter to both the DPLL NCO and

to the DPLL tuning word history. Thus, programming DPLL

history accumulation timer = 0 makes it possible to monitor

tuning words directly from the loop filter as they are applied to

the DPLL NCO. The DPLL history available status bit (Bit 0 of

Logic 0 when DPLL history accumulation timer = 0.

Changing the value of the DPLL history accumulation timer

exhibits different behavior depending on the current state of the

history circuit. The history processor only uses DPLL history

accumulation timer during holdoff and active operation, in

which case the history processor uses the new value (though

there may be a delay associated with the old value before the

update takes effect). The history circuit does not change states

upon a change of the value of the DPLL history accumulation

timer.

Updating the value of the DPLL history accumulation timer

while the history circuit is actively collecting history causes

future intervals to conform to the new value. If the elapsed

period of the current interval exceeds that of the new interval,

the next interval begins immediately. Otherwise, the current

interval conforms to the new value.

However, if the history circuit is in the holdoff state (see the

Averaging Processor Delay section), behavior is slightly

different. Because the history circuit averages over 1/8th

subintervals (see the Tuning Word Averaging Process section),

the progress of the averaging circuit matters. Specifically, the

number subintervals already completed remains unchanged

regardless of the actual time elapsed, and future subintervals

use the new period while the current subintervals continue to

use the old value.

Changing the DPLL history holdoff time value (see the Averaging

Processor Delay section) has no effect until the beginning of the

next holdoff period (in the entirety of the period, not a

subinterval). If the behavior associated with the holdoff period,

as a result of updating either the history period or the holdoff

value, must reflect the new value as soon as possible, the user can

restore the history circuit to its initialization state via the DPLL

clear history bit (see the DPLL Clear History Bit section).

Tuning Word Averaging Process

During operation, the averaging processor performs averaging

by partitioning the time span defined by the value of the DPLL

history accumulation timer into eight subintervals. During each

subinterval, the averaging processor computes the average of

the tuning word samples for that subinterval. A full tuning

word average, as defined by the value of the DPLL history

accumulation timer, constitutes the average of eight

consecutive subinterval averages.

At the termination of each successive subinterval (given the

averaging processor has set the DPLL history available status

bit), the averaging processor triggers the following events:

•

Update the rolling average computation

•

Save the result to the DPLL tuning word history

•

Update the DPLL history update status bit

As such, at the end of each subinterval, the averaging processor

stores the result of the updated rolling average computation in

the DPLL tuning word history. At the same time, the averaging

processor sets the DPLL history updated status bit to Logic 1.

The DPLL history updated status bit provides the user with a

AD9546/PCBZ Datasheet(PDF) 136 Page - Analog Devices

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