AD9546SLASHPCBZ datasheet(163/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 163 of 205

Auxiliary NCO Offset Frequency

Offset frequency assignment is via Bits[31:0] (unsigned) of

Bits[31:0] carry units of 2−24 Hz. The offset frequency value of

Bits[31:0] relates to the offset frequency, fOFFSET, as

fOFFSET = Offset Frequency Value × 2−24

For example, given a desired offset frequency of 100 Hz, find the

required 32-bit register value.

Offset Frequency Value = fOFFSET × 224

= 102 × 224

= 1,677,721,600

= 0x 6400 0000 (hexadecimal)

The offset frequency upper limit is 256 Hz (232 × 2−24 Hz).

The main purpose for the offset frequency is to give an external

processor or controller that is limited to 32-bit processing

capability the ability of rapidly changing the output frequency.

For example, it is cumbersome for a 32-bit machine to compute

the 56-bit center frequency and then deliver the computation to

the register map.

The 32-bit offset frequency option alleviates this problem

because the user can initially program an appropriate 56-bit

center frequency and then use 32-bit offset values to change the

output frequency. The 32-bit offset value allows a 32-bit

machine to operate in its native 32-bit environment and

facilitates rapid changing of the output frequency. The offset

values offer less precise tuning than the center frequency

(2−24 Hz vs. 2−40 Hz resolution).

Depending on the tuning range for a given application, the user

can use a combination of the center and offset values to minimize

the number of 8-bit registers required to cover the range, yet

still yield 2−40 Hz frequency resolution. For example, the user can

select a center and offset value that allows the offset to remain

fixed over the tuning range yet constrains tuning changes of the

center value to the lower 8, 16, 24, or 32 bits of the center

frequency value. Using only the LSBs of the center frequency

allows 32-bit (or less) register operations while still maintaining

2−40 Hz frequency tuning resolution.

AUXILIARY NCO PHASE OFFSET

The user can adjust the phase of the auxiliary NCO via

Bits[39:0] (signed, twos complement) in Register 0x2814 to

of the phase adjustment depends on the value of Bit 0 of

auxiliary NCO 1), as explained in the Absolute Phase Offset

section and the Relative Phase Offset section.

When the user programs Bits[39:0] and asserts the IO update

bit, the AD9546 automatically imposes a specified upper limit

on how fast the phase can change (phase slew). See the

Auxiliary NCO Phase Slew Limit section for details.

Absolute Phase Offset

Absolute phase offset adjustment is in effect when Bit 0 = 0 of

auxiliary NCO 1). For absolute phase offset adjustments, the phase

offset bits, Bits[39:0], constitute a signed absolute time offset with

1 ps resolution. The signed absolute time offset allows an offset

range of approximately ±0.55 sec (±10−12 sec × 239). However,

the user must limit programmed offset value to ±1 UI (that is,

plus or minus one period of the auxiliary NCO).

Note that programming a phase offset value in excess of the

±1 UI limit causes the device to set the status in Bit 5 or Bit 7 in

NCO 1, respectively.

For example, given a programmed auxiliary NCO 0 frequency

of 10 kHz (per the center frequency and offset frequency

settings) and a desired phase offset of −15.5°, determine the

necessary value of Bits[39:0] in Register 0x2814 to Register

0x2818, the absolute time offset.

First, ensure the phase offset is less than ±360° to satisfy the

±1 UI maximum phase offset requirement. The desired phase

offset of −15.5° is within the ±1 UI limit.

Next, determine the time, t, associated with a −15.5° phase

offset.

t = (−15.5°/360°)/(10 kHz)

= −4.3055555556 µs (to 10 decimal places)

Finally, convert the value of t to units of ps.

Bits[39:0] = t/(10−12 sec)

= (−4.3055555556 × 10−6 s)/(10−12 sec)

= −4,305,556 (nearest integer)

= 0x FF FFBE 4D6C (40-bit hexadecimal)

Relative Phase Offset

Relative phase offset adjustment is in effect when Bit 0 = 1 of

auxiliary NCO 1). For relative phase offset adjustments, the phase

offset bits, Bits[39:0], constitute a signed relative offset specified

as a fraction of the period of the auxiliary NCO. Thus, Bits[39:0]

cover a range from −½ UI to 1 LSB less than +½ UI.

For example, given a programmed auxiliary NCO 0 frequency

of 10 kHz (per the center frequency and offset frequency settings)

and a desired phase offset of −15.5°, determine the necessary

value of Bits[39:0] in Register 0x2814 to Register 0x2818, the

relative time offset.

First, the phase offset must be within ±180° to satisfy the ±½ UI

maximum offset requirement. The desired phase offset of

−15.5° is within the ±½ UI limit.

AD9546/PCBZ Datasheet(PDF) 163 Page - Analog Devices

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