AD9546SLASHPCBZ datasheet(169/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 169 of 205

SYSTEM CLOCK COMPENSATION

SYSTEM CLOCK COMPENSATION OVERVIEW

The NCOs and the TDCs of the AD9546 derive their

timekeeping from the system clock (see the System Clock PLL

section). Therefore, the frequency accuracy of any of the NCOs

relates directly to the accuracy of the system clock. Likewise, an

inferred frequency based on the difference between successive

TDC time stamps is subject to the accuracy of the system clock.

Therefore, the stability of the system clock is crucial to the

accuracy of the NCOs and TDCs within the AD9546.

The stability of the system clock, in turn, relates directly to the

stability of the system clock source. The system clock source is

the frequency source driving the XOA and XOB pins. As such,

an ideally stable system clock source is desirable. In practice,

however, the system clock source suffers from frequency

instability caused by aging, variations in temperature, and

similar physical factors. Any frequency instability introduced

by the system clock source translates to a frequency instability

in the NCOs and TDCs.

Because the NCOs and TDCs are fundamentally numeric (digital)

in nature, it is possible to tune the NCOs and TDCs

numerically to counteract the system clock instability. That is,

with a known frequency error associated with the system clock

source, the user can apply a corresponding correction

(numerically) to the NCOs and TDCs, which is the underlying

concept of system clock compensation.

The system clock compensation operates on fractional frequency

error (FFE) rather than absolute frequency error. For a given

nominal frequency, f0, the FFE of a deviated frequency, f, is

FFE = (f – f0)/f0

FFE = f/f0 − 1

In the case of TDCs, the difference between successive time

stamps is the period of the underlying frequency. The

difference between successive time stamps gives rise to the

concept of fractional period error (FPE).

FPE = (p − p0)/p0

FPE = p/p0 − 1

where:

p0 is the nominal period.

p is the deviated period.

Because frequency relates to period as f = 1/p, FFE and FPE

relate as follows:

FFE = −FPE/(FPE + 1)

FPE = −FFE/(FFE + 1)

In the context of system clock compensation, consider a given

system clock frequency error expressed in terms of FFE.

Applying an FFE correction factor to the NCOs and TDCs

compensates for the FFE error of the system clock source. FFE

as a correction factor to the NCOs and TDCs compensates for

the FFE of the system clock source. The AD9546 has the option

of applying system clock compensation via two methods: open-

loop method and closed-loop method.

Open-Loop Method

Figure 114 shows the open-loop method, with the system clock

source driving the system clock PLL, which in turn serves as the

clock source for a representative NCO within the AD9546.

Although Figure 114 shows an NCO, this section also applies to

a TDC.

fNCO

XOA XOB

fSRC

NCO

AD9546

SYSTEM

CLOCK PLL

COMPENSATION

CALCULATOR

FTW

1 + FFECOMP

CORRECTED

FTW

SYSTEM

CLOCK

SOURCE

Figure 114. Open-Loop Method

The system clock source provides the primary frequency, fSRC,

with a nominal value of f0. The system clock PLL, which is the

clock source to the NCO, multiplies fSRC by a constant, KPLL

(that is, fS = KPLL × fSRC). Assuming the FFE for system clock

compensation (FFECOMP) = 0 in Figure 114, the NCO produces an

output frequency, fNCO, proportional to the applied numeric

FTW (that is fNCO = fS × FTW × KNCO, where KNCO is the

proportionality constant). Therefore, express fNCO in terms of

fSRC as

fNCO = fSRC × KPLL × FTW × KNCO

The ideal (error free) fNCO is then

fNCO_IDEAL = f0 × KPLL × FTW × KNCO

where f0 is the nominal frequency of the system clock source. If

the system clock source experiences a fractional error, FFE,

fNCO = f0 × (1 + FFE) × KPLL × FTW × KNCO

Apply a fractional correction, FFECOMP, to compensate for FFE

as follows:

fNCO = f0 × (1 + FFE) × (1 + FFECOMP) × KPLL × FTW × KNCO

If FFECOMP = –FFE,

fNCO = f0 × (1 + FFE) × (1 – FFE) × KPLL × FTW × KNCO (24)

AD9546/PCBZ Datasheet(PDF) 169 Page - Analog Devices

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