AD9546SLASHPCBZ datasheet(195/205 Pages) AD

195 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 195 of 205

IEEE 1588 SERVO

The AD9546 provides the jitter cleaning, phase shifting, and

synchronization necessary for an IEEE 1588 servo and software

stack in a Telecom-BC (T-BC) with hybrid support application

(see Figure 131). Figure 131 represents a superset of possible

connection scenarios for implementing a variety of IEEE 1588

applications rather than a specific IEEE 1588 application. The

diagram in Figure 131 supports IEEE 1588 master and slave

clock operation. The dashed box in Figure 131 constitutes

external circuitry that handles precision time protocol (PTP)

packets, software to implement IEEE 1588, and time of day

support. The integrated features of the AD9546 simplify the

task of synchronizing clocks via PTP. Furthermore, the Mx pins

of the AD9546 provide the option to implement assisted partial

timing support (APTS) via a GPS receiver providing a precision

1 pps source.

Figure 131 implies the use of the AD9546 system clock

compensation feature (see the Compensation Method 3 section

in the System Clock Compensation section). Specifically, the

reference input serves as a frequency stable source to the system

clock compensation block (for example, an OXCO or TCXO).

The frequency stable source allows the AD9546 to use a crystal

resonator as the system clock source (XOA and XOB pins) and

compensate for the inherent crystal frequency instability,

thereby maintaining the overall timing precision of the system.

PLL0 uses the 125 MHz SyncE clock as a reference input to

generate two filtered, 125 MHz SyncE clocks. PLL1 uses one of

the auxiliary NCOs of the AD9546 as a reference input to

generate two arbitrary output clocks with stability

commensurate with the REF IN source. The system clock

compensation system ensures frequency stability of the NCOs

associated with the DPLLs and auxiliary NCOs.

The performance and feature set of the AD9546 make it ideal

for enabling the latest IEEE 1588 features, as well as the latest

ITU-T packet synchronization related standards for 4G and 5G

wireless networks.

MEMORY

CPU

MAC

PACKET

CLASSIFIER

AND

TIMESTAMP

TIME

DAY

CLOCK INTERFACES

MANAGEMENT

INTERFACE

SPI/I2C PORT

1PPS

125MHz FILTERED/ADJUSTED

CLOCK OUT

AUXILIARY CLOCK

OUTPUTS

(1PPS TO 500MHz)

RGMII/SGMII

(WITH SyncE SUPPORT)

REFERENCE

INPUT

125MHz (SyncE/CDR)

TIME OF DAY IN/OUT

(1PPS + UART WITH NEMA FORMAT)

XOA

DIGITAL CROSS

POINT MUX

DPLL0

MODULATION, PHASE

OFFSET, AND JESD204B

SYSTEM

CLOCK PLL

STATUS AND

CONTROL

PINS

SERIAL PORT

(SPI OR I2C)

AND EEPROM

CONTROLLER

AD9546

SYSTEM

CLOCK

TEMPERATURE

SENSOR

SYSTEM CLOCK

COMPENSATION

REFERENCE

MONITORS (8)

REFERENCE

SWITCHING CONTROL

INTERNAL

ZERO DELAY

2.424GHz TO 3.232GHz

TDC

DEMOD

3.232GHz TO 4.040GHz

DEMOD

USER TIME

STAMPS (9)

INVERSE

USER TIME

STAMPS (2)

AUXILIARY

NCO (2)

AUXILIARY REFERENCE (4)

COMMON CLOCK

SYNCHRONIZER

TDC

DEMOD

REFA/REFAA

REFA

REFAA

REFB

REFBB

XOB

OUT0Ax

OUT0Bx

OUT0Cx

OUT1Ax

OUT1Bx

CLOCK OUT

SERIAL PORT

Mx PINS

GPS

OPTIONAL

ASSISTED

PARTIAL

TIMING

SUPPORT

(APTS)

APLL0

REFB/REFBB

÷RA

÷RAA

DPLL1

APLL1

÷Q0A

÷Q0AA

÷Q0B

÷Q0BB

÷Q0C

÷Q0CC

÷Q1A

÷Q1AA

÷Q1B

÷Q1BB

125MHz FILTERED/ADJUSTED

÷R

Figure 131. Using an AD9546 in an IEEE 1588 Version 2 Application

AD9546/PCBZ Datasheet(PDF) 195 Page - Analog Devices

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