ICS650-07B

Broadcom Clock Source

MD S 650-07B A

3

Revision 042600

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (n

note 1)

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 20 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH, X1 pin only

VDD/2 + 1

VDD/2

V

Input Low Voltage, VIL, X1 pin only

VDD/2

VDD/2 - 1

V

Input High Voltage, VIH, PS pin only

VDD-0.5

V

Input Low Voltage, VIL, PS pin only

0.5

V

Output High Voltage, VOH

IOH=-12 mA

2.4

V

Output Low Voltage, VOL

IOL=12 mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-4 mA

VDD-0.4

V

Operating Supply Current, IDD

No Load

35

mA

Short Circuit Current

Each output

±50

mA

Internal pull-up resistor

PS, OE

200

k

Ω

AC CHARACTERISTICS (VDD = 3.3 V

V unless noted)

Input Frequency

25.000

MHz

Output Clock Rise Time

0.8 to 2.0 V

1.5

ns

Output Clock Fall Time

2.0 to 0.8 V

1.5

ns

Output Clock Duty Cycle

At VDD/2

40

50

60

%

Frequency error

All clocks

0

ppm

Absolute Jitter, short term

Variation from mean

±200

ps

Electrical Specifications

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

External Components

The ICS650-07B requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between each VDD and GND, as close to the ICS650-07B as

possible. A series termination resistor of 33

Ω may be used for each clock output. The 25.00 MHz crystal

must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use

third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2

to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation,

capacitance, two 20 pF caps should be used.